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83 lines
2.0 KiB
Verilog
83 lines
2.0 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// EMI mitigation.
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// Process FULL flag from FIFO so that de-assertion
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// (FIFO now not FULL) is delayed by a pseudo random
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// value, but assertion is passed straight through.
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//
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module refill_randomizer
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#(parameter BITS=7)
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(
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input clk,
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input rst,
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input full_in,
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output full_out
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);
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wire feedback;
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reg full_last;
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wire full_deasserts;
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reg [6:0] shift_reg;
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reg [6:0] count;
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reg delayed_fall;
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always @(posedge clk)
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full_last <= full_in;
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assign full_deasserts = full_last & ~full_in;
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// 7 bit LFSR
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always @(posedge clk)
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if (rst)
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shift_reg <= 7'b1;
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else
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if (full_deasserts)
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shift_reg <= {shift_reg[5:0],feedback};
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assign feedback = ^(shift_reg & 7'h41);
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always @(posedge clk)
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if (rst)
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begin
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count <= 1;
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delayed_fall <= 1;
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end
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else if (full_deasserts)
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begin
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count <= shift_reg;
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delayed_fall <= 1;
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end
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else if (count == 1)
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begin
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count <= 1;
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delayed_fall <= 0;
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end
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else
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begin
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count <= count - 1;
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delayed_fall <= 1;
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end
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// Full_out goes instantly high if full_in does. However its fall is delayed.
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assign full_out = (full_in == 1) || (full_last == 1) || delayed_fall;
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endmodule |