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https://github.com/fairwaves/UHD-Fairwaves.git
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95 lines
2.9 KiB
Verilog
95 lines
2.9 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Dual ported, Harvard architecture
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module ram_harvard2
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#(parameter AWIDTH=15,
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parameter RAM_SIZE=32768)
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(input wb_clk_i,
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input wb_rst_i,
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// Instruction fetch port.
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input [AWIDTH-1:0] if_adr,
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output reg [31:0] if_data,
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// Data access port.
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input [AWIDTH-1:0] dwb_adr_i,
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input [31:0] dwb_dat_i,
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output reg [31:0] dwb_dat_o,
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input dwb_we_i,
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output dwb_ack_o,
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input dwb_stb_i,
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input [3:0] dwb_sel_i);
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reg ack_d1;
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reg stb_d1;
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assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
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always @(posedge wb_clk_i)
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if(wb_rst_i)
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ack_d1 <= 1'b0;
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else
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ack_d1 <= dwb_ack_o;
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always @(posedge wb_clk_i)
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if(wb_rst_i)
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stb_d1 <= 0;
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else
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stb_d1 <= dwb_stb_i;
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reg [7:0] ram0 [0:(RAM_SIZE/4)-1];
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reg [7:0] ram1 [0:(RAM_SIZE/4)-1];
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reg [7:0] ram2 [0:(RAM_SIZE/4)-1];
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reg [7:0] ram3 [0:(RAM_SIZE/4)-1];
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// Port 1, Read only
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always @(posedge wb_clk_i)
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if_data[31:24] <= ram3[if_adr[AWIDTH-1:2]];
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always @(posedge wb_clk_i)
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if_data[23:16] <= ram2[if_adr[AWIDTH-1:2]];
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always @(posedge wb_clk_i)
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if_data[15:8] <= ram1[if_adr[AWIDTH-1:2]];
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always @(posedge wb_clk_i)
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if_data[7:0] <= ram0[if_adr[AWIDTH-1:2]];
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// Port 2, R/W
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always @(posedge wb_clk_i)
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if(dwb_stb_i) dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]];
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always @(posedge wb_clk_i)
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if(dwb_stb_i) dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]];
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always @(posedge wb_clk_i)
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if(dwb_stb_i) dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]];
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always @(posedge wb_clk_i)
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if(dwb_stb_i) dwb_dat_o[7:0] <= ram0[dwb_adr_i[AWIDTH-1:2]];
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always @(posedge wb_clk_i)
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if(dwb_we_i & dwb_stb_i & dwb_sel_i[3])
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ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24];
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always @(posedge wb_clk_i)
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if(dwb_we_i & dwb_stb_i & dwb_sel_i[2])
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ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16];
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always @(posedge wb_clk_i)
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if(dwb_we_i & dwb_stb_i & dwb_sel_i[1])
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ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8];
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always @(posedge wb_clk_i)
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if(dwb_we_i & dwb_stb_i & dwb_sel_i[0])
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ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0];
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endmodule // ram_harvard
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