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78 lines
2.2 KiB
Verilog
78 lines
2.2 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module simple_uart_tx
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#(parameter DEPTH=0)
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(input clk, input rst,
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input [7:0] fifo_in, input fifo_write, output [7:0] fifo_level, output fifo_full,
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input [15:0] clkdiv, output baudclk, output reg tx);
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reg [15:0] baud_ctr;
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reg [3:0] bit_ctr;
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wire read, empty;
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wire [7:0] char_to_send;
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medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo
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(.clk(clk),.rst(rst),
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.datain(fifo_in),.write(fifo_write),.full(fifo_full),
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.dataout(char_to_send),.read(read),.empty(empty),
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.clear(0),.space(fifo_level),.occupied() );
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always @(posedge clk)
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if(rst)
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baud_ctr <= 0;
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else if (baud_ctr >= clkdiv)
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baud_ctr <= 0;
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else
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baud_ctr <= baud_ctr + 1;
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always @(posedge clk)
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if(rst)
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bit_ctr <= 0;
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else if(baud_ctr == clkdiv)
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if(bit_ctr == 9)
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bit_ctr <= 0;
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else if(bit_ctr != 0)
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bit_ctr <= bit_ctr + 1;
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else if(~empty)
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bit_ctr <= 1;
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always @(posedge clk)
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if(rst)
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tx <= 1;
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else
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case(bit_ctr)
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0 : tx <= 1;
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1 : tx <= 0;
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2 : tx <= char_to_send[0];
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3 : tx <= char_to_send[1];
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4 : tx <= char_to_send[2];
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5 : tx <= char_to_send[3];
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6 : tx <= char_to_send[4];
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7 : tx <= char_to_send[5];
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8 : tx <= char_to_send[6];
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9 : tx <= char_to_send[7];
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default : tx <= 1;
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endcase // case(bit_ctr)
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assign read = (bit_ctr == 9) && (baud_ctr == clkdiv);
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assign baudclk = (baud_ctr == 1); // Only for debug purposes
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endmodule // simple_uart_tx
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