mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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100 lines
2.9 KiB
Verilog
100 lines
2.9 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module fifo_tb();
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reg clk = 0;
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reg rst = 1;
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reg clear = 0;
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initial #1000 rst = 0;
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always #50 clk = ~clk;
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reg [18:0] f19a;
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wire [18:0] f19b, f19c, f19d;
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wire [35:0] f36a, f36b;
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reg f19a_sr = 0;
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wire f19b_sr, f19c_sr, f19d_sr, f36a_sr, f36b_sr;
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wire f19a_dr, f19b_dr, f19c_dr, f19d_dr, f36a_dr, f36b_dr;
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fifo_short #(.WIDTH(19)) fifo_short1
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(.clk(clk),.reset(rst),.clear(clear),
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.datain(f19a),.src_rdy_i(f19a_sr),.dst_rdy_o(f19a_dr),
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.dataout(f19b),.src_rdy_o(f19b_sr),.dst_rdy_i(f19b_dr) );
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fifo19_to_fifo36 fifo19_to_fifo36
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(.clk(clk),.reset(rst),.clear(clear),
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.f19_datain(f19b),.f19_src_rdy_i(f19b_sr),.f19_dst_rdy_o(f19b_dr),
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.f36_dataout(f36a),.f36_src_rdy_o(f36a_sr),.f36_dst_rdy_i(f36a_dr) );
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fifo_short #(.WIDTH(36)) fifo_short2
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(.clk(clk),.reset(rst),.clear(clear),
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.datain(f36a),.src_rdy_i(f36a_sr),.dst_rdy_o(f36a_dr),
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.dataout(f36b),.src_rdy_o(f36b_sr),.dst_rdy_i(f36b_dr) );
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fifo36_to_fifo19 fifo36_to_fifo19
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(.clk(clk),.reset(rst),.clear(clear),
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.f36_datain(f36b),.f36_src_rdy_i(f36b_sr),.f36_dst_rdy_o(f36b_dr),
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.f19_dataout(f19c),.f19_src_rdy_o(f19c_sr),.f19_dst_rdy_i(f19c_dr) );
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fifo_short #(.WIDTH(19)) fifo_short3
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(.clk(clk),.reset(rst),.clear(clear),
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.datain(f19c),.src_rdy_i(f19c_sr),.dst_rdy_o(f19c_dr),
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.dataout(f19d),.src_rdy_o(f19d_sr),.dst_rdy_i(f19d_dr) );
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assign f19d_dr = 1;
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always @(posedge clk)
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if(f19a_sr & f19a_dr)
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$display("18IN: %h", f19a);
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always @(posedge clk)
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if(f19d_sr & f19d_dr)
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$display(" 18OUT: %h", f19d);
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always @(posedge clk)
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if(f36b_sr & f36b_dr)
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$display(" 36: %h", f36b);
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initial $dumpfile("fifo_tb.vcd");
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initial $dumpvars(0,fifo_tb);
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initial
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begin
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@(negedge rst);
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@(posedge clk);
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repeat (2)
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begin
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f19a <= 19'h1_AA01;
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f19a_sr <= 1;
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@(posedge clk);
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f19a <= 19'h0_AA02;
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repeat (4)
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begin
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@(posedge clk);
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f19a <= f19a + 1;
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end
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f19a[18:16] <= 3'b010;
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@(posedge clk);
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f19a_sr <= 0;
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f19a <= 19'h7_FFFF;
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@(posedge clk);
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end
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#20000 $finish;
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end
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endmodule // longfifo_tb
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