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37 lines
938 B
Plaintext
37 lines
938 B
Plaintext
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FIFO and Buffer Interface Spec
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Buffer Interface Data Wires -- matches fifo36
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DATA[31:0]
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FLAGS[3:0]
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Bit 0 SOP
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Bit 1 EOP
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If SOP=1 && EOP=1, OCC contains error flags
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Bits 3:2 OCC[1:0] --> 00 = all 4 bytes
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01 = 1 byte
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10 = 2 bytes
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11 = 3 bytes
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fifo36 --> {OCC[1:0],EOP,SOP,DATA[31:0]}
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OCC same as buffer interface
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fifo19 --> {OCC,EOP,SOP,DATA[15:0]}
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Doesn't fit well into BRAM, dist RAM ok
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OCC = 1 means last word is half full
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= 0 means last word is full
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fifo18 --> {EOP,SOP,DATA[15:0]}
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No half-word capability? Should we drop sop instead?
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Control Wires - Data into FIFO
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SRC_RDY_i Upstream has data for me
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DST_RDY_o I have space
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Transfer occurs if SRC_RDI_i && DST_RDY_o
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Control Wires - Data out of FIFO
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SRC_RDY_o I have data for downstream
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DST_RDY_i Downstream has space
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Transfer occurs if SRC_RDI_o && DST_RDY_i
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