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54 lines
1.3 KiB
Verilog
54 lines
1.3 KiB
Verilog
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E.v,v 1.7 2005/03/14 22:32:58 yanx Exp $
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 8.1i (I.13)
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// \ \ Description : Xilinx Functional Simulation Library Component
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// / / 16-Bit Shift Register Look-Up-Table with Clock Enable
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// /___/ /\ Filename : SRL16E.v
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// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// End Revision
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`timescale 1 ps / 1 ps
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module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D);
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parameter INIT = 16'h0000;
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output Q;
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input A0, A1, A2, A3, CE, CLK, D;
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reg [15:0] data;
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assign Q = data[{A3, A2, A1, A0}];
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initial
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begin
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assign data = INIT;
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while (CLK === 1'b1 || CLK===1'bX)
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#10;
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deassign data;
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end
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always @(posedge CLK)
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begin
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if (CE == 1'b1) begin
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{data[15:0]} <= #100 {data[14:0], D};
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end
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end
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endmodule
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