mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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114 lines
2.5 KiB
Verilog
114 lines
2.5 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module cpld_model
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(input aux_clk, input start, input mode, input done,
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output dout, output reg sclk, output detached);
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reg [7:0] rom[0:65535];
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reg [15:0] addr;
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reg [7:0] data;
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assign dout = data[7];
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reg [2:0] state, bitcnt;
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localparam IDLE = 3'd0;
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localparam READ = 3'd1;
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localparam BIT1 = 3'd2;
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localparam BIT2 = 3'd3;
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localparam DONE = 3'd4;
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localparam DETACHED = 3'd5;
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localparam ERROR = 3'd7;
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integer i;
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reg [1023:0] ROMFile;
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initial begin
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for (i=0;i<65536;i=i+1) begin
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rom[i] <= 32'h0;
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end
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if ( !$value$plusargs( "rom=%s", ROMFile ) )
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begin
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$display( "Using default ROM file, 'flash.rom'" );
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ROMFile = "flash.rom";
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end
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else
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$display( "Using %s as ROM file.", ROMFile);
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#1 $readmemh( ROMFile,rom );
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end
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initial addr = 16'd0;
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initial data = 8'd0;
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initial state = IDLE;
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initial bitcnt = 3'd0;
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initial sclk = 1'b0;
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always @(posedge aux_clk)
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case(state)
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IDLE :
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if(start)
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if(~mode)
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state <= READ;
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else
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state <= ERROR;
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READ :
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if(done)
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state <= DONE;
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else
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begin
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data <= rom[addr];
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addr <= addr + 1;
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bitcnt <= 3'd0;
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if(addr==16'hFFFF)
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state <= ERROR;
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else
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state <= BIT1;
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end // else: !if(start)
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BIT1 :
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begin
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sclk <= 1'b1;
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state <= BIT2;
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end
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BIT2 :
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begin
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sclk <= 1'b0;
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data <= {data[6:0],1'b0};
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bitcnt <= bitcnt + 1;
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if(bitcnt==7)
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state <= READ;
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else
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state <=BIT1;
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end
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DONE :
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begin
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if(start)
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state <= ERROR;
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else
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state <= DETACHED;
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end
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DETACHED :
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if(start)
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state <= ERROR;
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endcase // case(state)
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assign detached = (state == DETACHED) || (state == IDLE);
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endmodule // cpld_model
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