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52 lines
1.5 KiB
Verilog
52 lines
1.5 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module serdes_model
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(input ser_tx_clk,
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input ser_tkmsb,
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input ser_tklsb,
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input [15:0] ser_t,
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output ser_rx_clk,
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output ser_rkmsb,
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output ser_rklsb,
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output [15:0] ser_r,
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input even,
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input error);
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wire [15:0] ser_r_odd;
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wire ser_rklsb_odd, ser_rkmsb_odd;
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reg [7:0] hold_dat;
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reg hold_k;
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always @(posedge ser_tx_clk) hold_k <= ser_tklsb;
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always @(posedge ser_tx_clk) hold_dat <= ser_t[15:8];
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assign ser_rklsb_odd = hold_k;
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assign ser_rkmsb_odd = ser_tklsb;
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assign ser_r_odd = {ser_t[7:0], hold_dat};
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// Set outputs
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assign ser_rx_clk = ser_tx_clk;
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assign ser_rkmsb = even ? ser_tkmsb : ser_rkmsb_odd;
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assign ser_rklsb = even ? ser_tklsb : ser_rklsb_odd;
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assign ser_r = error ^ (even ? ser_t : ser_r_odd);
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endmodule // serdes_model
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