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60 lines
1.7 KiB
Verilog
60 lines
1.7 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// up to 8 semaphores
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// After a read operation, the semaphore is always locked
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// If it was already locked before the read (meaning someone else holds the lock)
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// then a 1 is returned
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// If it was not already locked (meaning the reader now holds the lock)
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// then a 0 is returned
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// A write operation clears the lock
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module wb_semaphore
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#(parameter count=8, DBUS_WIDTH=32)
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(input wb_clk_i,
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input wb_rst_i,
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input [DBUS_WIDTH-1:0] wb_dat_i,
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input [2:0] wb_adr_i,
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input wb_cyc_i,
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input wb_stb_i,
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input wb_we_i,
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output wb_ack_o,
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output [DBUS_WIDTH-1:0] wb_dat_o);
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reg [count-1:0] locked;
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always @(posedge clock)
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if(wb_rst_i)
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locked <= {count{1'b0}};
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else if(wb_stb_i)
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if(wb_we_i)
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locked[adr_i] <= 1'b0;
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else
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locked[adr_i] <= 1'b1;
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assign wb_dat_o[DBUS_WIDTH-1:1] = {(DBUS_WIDTH-1){1'b0}};
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assign wb_dat_o[0] = locked[adr_i];
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assign wb_ack_o = wb_stb_i;
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endmodule // wb_semaphore
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