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30 lines
972 B
Verilog
30 lines
972 B
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module add_onescomp
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#(parameter WIDTH = 16)
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(input [WIDTH-1:0] A,
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input [WIDTH-1:0] B,
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output [WIDTH-1:0] SUM);
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wire [WIDTH:0] SUM_INT = {1'b0,A} + {1'b0,B};
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assign SUM = SUM_INT[WIDTH-1:0] + {{WIDTH-1{1'b0}},SUM_INT[WIDTH]};
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endmodule // add_onescomp
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