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45 lines
1.4 KiB
Verilog
45 lines
1.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module packet32_tb();
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wire [35:0] data;
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wire src_rdy, dst_rdy;
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wire clear = 0;
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reg clk = 0;
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reg reset = 1;
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always #10 clk <= ~clk;
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initial #1000 reset <= 0;
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initial $dumpfile("packet32_tb.vcd");
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initial $dumpvars(0,packet32_tb);
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wire [31:0] total, crc_err, seq_err, len_err;
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packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear),
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.data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
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packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear),
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.data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
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.total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
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endmodule // packet32_tb
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