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101 lines
3.0 KiB
Verilog
101 lines
3.0 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module packet_generator
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(input clk, input reset, input clear,
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output reg [7:0] data_o, output sof_o, output eof_o,
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input [127:0] header,
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output src_rdy_o, input dst_rdy_i);
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localparam len = 32'd2000;
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reg [31:0] state;
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reg [31:0] seq;
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reg [31:0] crc_out;
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wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
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always @(posedge clk)
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if(reset | clear)
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seq <= 0;
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else
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if(eof_o & src_rdy_o & dst_rdy_i)
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seq <= seq + 1;
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always @(posedge clk)
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if(reset | clear)
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state <= 0;
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else
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if(src_rdy_o & dst_rdy_i)
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if(state == (len - 1))
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state <= 32'hFFFF_FFFC;
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else
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state <= state + 1;
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always @*
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case(state)
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0 : data_o <= len[31:24];
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1 : data_o <= len[23:16];
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2 : data_o <= len[15:8];
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3 : data_o <= len[7:0];
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4 : data_o <= seq[31:24];
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5 : data_o <= seq[23:16];
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6 : data_o <= seq[15:8];
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7 : data_o <= seq[7:0];
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8 : data_o <= header[7:0];
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9 : data_o <= header[15:8];
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10 : data_o <= header[23:16];
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11 : data_o <= header[31:24];
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12 : data_o <= header[39:32];
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13 : data_o <= header[47:40];
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14 : data_o <= header[55:48];
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15 : data_o <= header[63:56];
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16 : data_o <= header[71:64];
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17 : data_o <= header[79:72];
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18 : data_o <= header[87:80];
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19 : data_o <= header[95:88];
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20 : data_o <= header[103:96];
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21 : data_o <= header[111:104];
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22 : data_o <= header[119:112];
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23 : data_o <= header[127:120];
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32'hFFFF_FFFC : data_o <= crc_out[31:24];
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32'hFFFF_FFFD : data_o <= crc_out[23:16];
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32'hFFFF_FFFE : data_o <= crc_out[15:8];
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32'hFFFF_FFFF : data_o <= crc_out[7:0];
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default : data_o <= state[7:0];
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endcase // case (state)
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assign src_rdy_o = 1;
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assign sof_o = (state == 0);
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assign eof_o = (state == 32'hFFFF_FFFF);
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wire clear_crc = eof_o & src_rdy_o & dst_rdy_i;
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// crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o),
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// .calc(calc_crc), .crc_out(crc_out), .match());
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always @(posedge clk)
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if(reset | clear | clear_crc)
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crc_out <= 0;
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else
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if(calc_crc)
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crc_out <= crc_out + data_o;
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endmodule // packet_generator
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