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72 lines
2.5 KiB
Verilog
72 lines
2.5 KiB
Verilog
// Copyright 2013 Fairwaves
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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module frontend_sw
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#(parameter BASE=0)
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(input clk, input rst,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input [23:0] i_0_in, input [23:0] q_0_in,
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input [23:0] i_1_in, input [23:0] q_1_in,
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input run_0_in, input run_1_in,
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input adc_ovf_i_0_in, input adc_ovf_q_0_in,
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input adc_ovf_i_1_in, input adc_ovf_q_1_in,
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output reg [23:0] i_0_mux, output reg [23:0] q_0_mux,
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output reg [23:0] i_1_mux, output reg [23:0] q_1_mux,
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output reg run_0_mux, output reg run_1_mux,
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output reg adc_ovf_i_0_mux, output reg adc_ovf_q_0_mux,
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output reg adc_ovf_i_1_mux, output reg adc_ovf_q_1_mux);
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wire front_sw;
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setting_reg #(.my_addr(BASE),.width(1), .at_reset(32'd0)) sr_front_sw
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(.clk(clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out(front_sw),.changed());
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always @(posedge clk)
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if(~front_sw)
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begin
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i_0_mux <= i_0_in;
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q_0_mux <= q_0_in;
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i_1_mux <= i_1_in;
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q_1_mux <= q_1_in;
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run_0_mux <= run_0_in;
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run_1_mux <= run_1_in;
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adc_ovf_i_0_mux <= adc_ovf_i_0_in;
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adc_ovf_q_0_mux <= adc_ovf_q_0_in;
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adc_ovf_i_1_mux <= adc_ovf_i_1_in;
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adc_ovf_q_1_mux <= adc_ovf_q_1_in;
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end
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else
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begin
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i_0_mux <= i_1_in;
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q_0_mux <= q_1_in;
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i_1_mux <= i_0_in;
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q_1_mux <= q_0_in;
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run_0_mux <= run_1_in;
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run_1_mux <= run_0_in;
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adc_ovf_i_0_mux <= adc_ovf_i_1_in;
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adc_ovf_q_0_mux <= adc_ovf_q_1_in;
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adc_ovf_i_1_mux <= adc_ovf_i_0_in;
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adc_ovf_q_1_mux <= adc_ovf_q_0_in;
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end
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endmodule
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