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113 lines
3.3 KiB
Verilog
113 lines
3.3 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Medium halfband decimator (intended to be followed by another stage)
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// Implements impulse responses of the form [A 0 B 0 C 0 D 0.5 D 0 C 0 B 0 A]
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//
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// These taps designed by halfgen_test:
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// 2 * 131072 * halfgen_test(.8/8,4,1)
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// -597, 0, 4283, 0, -17516, 0, 79365, 131072, 79365, 0, -17516, 0, 4283, 0, -597
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module med_hb_int
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#(parameter WIDTH=18)
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(input clk,
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input rst,
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input bypass,
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input stb_in,
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input [WIDTH-1:0] data_in,
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input [7:0] output_rate,
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input stb_out,
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output reg [WIDTH-1:0] data_out);
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localparam coeff_a = -597;
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localparam coeff_b = 4283;
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localparam coeff_c = -17516;
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localparam coeff_d = 79365;
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reg phase;
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reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6, d7, d8;
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localparam MWIDTH = 36;
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wire [MWIDTH-1:0] prod;
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reg [6:0] stbin_d;
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always @(posedge clk)
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stbin_d <= {stbin_d[5:0],stb_in};
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always @(posedge clk)
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if(stb_in)
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begin
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d1 <= data_in;
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d2 <= d1;
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d3 <= d2;
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d4 <= d3;
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d5 <= d4;
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d6 <= d5;
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d7 <= d6;
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d8 <= d7;
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end
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wire [WIDTH-1:0] sum_a, sum_b, sum_c, sum_d;
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add2_and_round_reg #(.WIDTH(WIDTH)) add_a (.clk(clk),.in1(d1),.in2(d8),.sum(sum_a));
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add2_and_round_reg #(.WIDTH(WIDTH)) add_b (.clk(clk),.in1(d2),.in2(d7),.sum(sum_b));
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add2_and_round_reg #(.WIDTH(WIDTH)) add_c (.clk(clk),.in1(d3),.in2(d6),.sum(sum_c));
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add2_and_round_reg #(.WIDTH(WIDTH)) add_d (.clk(clk),.in1(d4),.in2(d5),.sum(sum_d));
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MULT18X18S mult1(.C(clk), .CE(1), .R(rst), .P(prod1), .A(stbin_d[1] ? coeff_a : coeff_b),
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.B(stbin_d[1] ? sum_a : sum_b) );
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MULT18X18S mult2(.C(clk), .CE(1), .R(rst), .P(prod2), .A(stbin_d[1] ? coeff_c : coeff_d),
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.B(stbin_d[1] ? sum_c : sum_d) );
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wire [MWIDTH:0] accum;
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acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1))
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acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum));
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wire [WIDTH+2:0] accum_rnd;
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round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3))
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final_round (.clk(clk),.in(accum),.out(accum_rnd));
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wire [WIDTH-1:0] clipped;
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clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH))
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final_clip (.clk(clk),.in(accum_rnd),.out(clipped));
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reg [WIDTH-1:0] saved, saved_d3;
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always @(posedge clk)
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if(stbin_d[6])
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saved <= clipped;
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always @(posedge clk)
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if(stbin_d[3])
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saved_d3 <= d3;
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always @(posedge clk)
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if(bypass)
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data_out <= data_in;
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else if(stb_in & stb_out)
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case(output_rate)
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1 : data_out <= d6;
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2 : data_out <= d4;
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3, 4, 5, 6, 7 : data_out <= d3;
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default : data_out <= d2;
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endcase // case(output_rate)
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else if(stb_out)
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data_out <= saved;
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endmodule // small_hb_int
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