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396 lines
14 KiB
Verilog
396 lines
14 KiB
Verilog
//
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// Copyright 2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// A settings and readback bus controlled via fifo36 interface
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module settings_fifo_ctrl
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#(
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parameter XPORT_HDR = 1, //extra transport hdr line
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parameter PROT_DEST = 0, //protocol framer destination
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parameter PROT_HDR = 1, //needs a protocol header?
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parameter ACK_SID = 0 //stream ID for packet ACK
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)
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(
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//clock and synchronous reset for all interfaces
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input clock, input reset, input clear,
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//current system time
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input [63:0] vita_time,
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//ready signal for multiple peripherals
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input perfs_ready,
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//input fifo36 interface control
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input [35:0] in_data, input in_valid, output in_ready,
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//output fifo36 interface status
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output [35:0] out_data, output out_valid, input out_ready,
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//32-bit settings bus outputs
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output strobe, output [7:0] addr, output [31:0] data,
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//16X 32-bit inputs for readback
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input [31:0] word00,
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input [31:0] word01,
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input [31:0] word02,
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input [31:0] word03,
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input [31:0] word04,
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input [31:0] word05,
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input [31:0] word06,
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input [31:0] word07,
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input [31:0] word08,
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input [31:0] word09,
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input [31:0] word10,
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input [31:0] word11,
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input [31:0] word12,
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input [31:0] word13,
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input [31:0] word14,
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input [31:0] word15,
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//debug output
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output [31:0] debug
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);
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wire reading = in_valid && in_ready;
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wire writing = out_valid && out_ready;
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//------------------------------------------------------------------
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//-- The command fifo:
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//-- Stores an individual register access command per line.
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//------------------------------------------------------------------
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wire [63:0] in_command_ticks, out_command_ticks;
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wire [31:0] in_command_hdr, out_command_hdr;
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wire [31:0] in_command_data, out_command_data;
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wire in_command_has_time, out_command_has_time;
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wire command_fifo_full, command_fifo_empty;
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wire command_fifo_read, command_fifo_write;
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shortfifo #(.WIDTH(129)) command_fifo (
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.clk(clock), .rst(reset), .clear(clear),
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.datain({in_command_ticks, in_command_hdr, in_command_data, in_command_has_time}),
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.dataout({out_command_ticks, out_command_hdr, out_command_data, out_command_has_time}),
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.write(command_fifo_write), .full(command_fifo_full), //input interface
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.empty(command_fifo_empty), .read(command_fifo_read) //output interface
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);
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//------------------------------------------------------------------
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//-- The result fifo:
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//-- Stores an individual result of a command per line.
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//------------------------------------------------------------------
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wire [31:0] in_result_hdr, out_result_hdr;
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wire [31:0] in_result_data, out_result_data;
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wire result_fifo_full, result_fifo_empty;
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wire result_fifo_read, result_fifo_write;
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shortfifo #(.WIDTH(64)) result_fifo (
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.clk(clock), .rst(reset), .clear(clear),
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.datain({in_result_hdr, in_result_data}),
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.dataout({out_result_hdr, out_result_data}),
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.write(result_fifo_write), .full(result_fifo_full), //input interface
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.empty(result_fifo_empty), .read(result_fifo_read) //output interface
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);
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//------------------------------------------------------------------
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//-- Input state machine:
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//-- Read input packet and fill a command fifo entry.
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//------------------------------------------------------------------
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localparam READ_LINE0 = 0;
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localparam VITA_HDR = 1;
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localparam VITA_SID = 2;
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localparam VITA_CID0 = 3;
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localparam VITA_CID1 = 4;
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localparam VITA_TSI = 5;
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localparam VITA_TSF0 = 6;
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localparam VITA_TSF1 = 7;
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localparam READ_HDR = 8;
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localparam READ_DATA = 9;
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localparam WAIT_EOF = 10;
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localparam STORE_CMD = 11;
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localparam START_STATE = (XPORT_HDR)? READ_LINE0 : VITA_HDR;
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reg [4:0] in_state;
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//holdover from current read inputs
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reg [31:0] in_data_reg, in_hdr_reg;
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reg [63:0] in_ticks_reg;
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wire has_sid = in_data[28];
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wire has_cid = in_data[27];
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wire has_tsi = in_data[23:22] != 0;
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wire has_tsf = in_data[21:20] != 0;
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reg has_sid_reg, has_cid_reg, has_tsi_reg, has_tsf_reg;
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assign in_ready = (in_state < STORE_CMD);
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assign command_fifo_write = (in_state == STORE_CMD);
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assign in_command_ticks = in_ticks_reg;
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assign in_command_data = in_data_reg;
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assign in_command_hdr = in_hdr_reg;
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assign in_command_has_time = has_tsf_reg;
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always @(posedge clock) begin
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if (reset) begin
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in_state <= START_STATE;
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end
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else begin
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case (in_state)
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READ_LINE0: begin
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if (reading) in_state <= VITA_HDR;
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end
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VITA_HDR: begin
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if (reading) begin
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if (has_sid) in_state <= VITA_SID;
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else if (has_cid) in_state <= VITA_CID0;
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else if (has_tsi) in_state <= VITA_TSI;
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else if (has_tsf) in_state <= VITA_TSF0;
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else in_state <= READ_HDR;
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end
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has_sid_reg <= has_sid;
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has_cid_reg <= has_cid;
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has_tsi_reg <= has_tsi;
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has_tsf_reg <= has_tsf;
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end
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VITA_SID: begin
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if (reading) begin
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if (has_cid_reg) in_state <= VITA_CID0;
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else if (has_tsi_reg) in_state <= VITA_TSI;
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else if (has_tsf_reg) in_state <= VITA_TSF0;
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else in_state <= READ_HDR;
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end
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end
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VITA_CID0: begin
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if (reading) in_state <= VITA_CID1;
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end
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VITA_CID1: begin
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if (reading) begin
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if (has_tsi_reg) in_state <= VITA_TSI;
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else if (has_tsf_reg) in_state <= VITA_TSF0;
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else in_state <= READ_HDR;
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end
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end
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VITA_TSI: begin
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if (reading) begin
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if (has_tsf_reg) in_state <= VITA_TSF0;
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else in_state <= READ_HDR;
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end
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end
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VITA_TSF0: begin
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if (reading) in_state <= VITA_TSF1;
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in_ticks_reg[63:32] <= in_data;
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end
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VITA_TSF1: begin
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if (reading) in_state <= READ_HDR;
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in_ticks_reg[31:0] <= in_data;
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end
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READ_HDR: begin
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if (reading) in_state <= READ_DATA;
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in_hdr_reg <= in_data[31:0];
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end
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READ_DATA: begin
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if (reading) in_state <= (in_data[33])? STORE_CMD : WAIT_EOF;
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in_data_reg <= in_data[31:0];
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end
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WAIT_EOF: begin
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if (reading && in_data[33]) in_state <= STORE_CMD;
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end
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STORE_CMD: begin
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if (~command_fifo_full) in_state <= START_STATE;
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end
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endcase //in_state
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end
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end
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//------------------------------------------------------------------
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//-- Command state machine:
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//-- Read a command fifo entry, act on it, produce result.
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//------------------------------------------------------------------
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localparam LOAD_CMD = 0;
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localparam EVENT_CMD = 1;
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reg cmd_state;
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reg [31:0] rb_data;
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reg [63:0] command_ticks_reg;
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reg [31:0] command_hdr_reg;
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reg [31:0] command_data_reg;
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reg [63:0] vita_time_reg;
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always @(posedge clock)
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vita_time_reg <= vita_time;
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wire late;
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`ifndef FIFO_CTRL_NO_TIME
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time_compare time_compare(
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.time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late));
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`else
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assign late = 1;
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`endif
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//action occurs in the event state and when there is fifo space (should always be true)
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//the third condition is that all peripherals in the perfs signal are ready/active high
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//the fourth condition is that is an event time has been set, action is delayed until that time
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wire time_ready = (out_command_has_time)? late : 1;
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wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && perfs_ready && time_ready;
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assign command_fifo_read = action;
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assign result_fifo_write = action;
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assign in_result_hdr = command_hdr_reg;
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assign in_result_data = rb_data;
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always @(posedge clock) begin
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if (reset) begin
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cmd_state <= LOAD_CMD;
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end
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else begin
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case (cmd_state)
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LOAD_CMD: begin
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if (~command_fifo_empty) cmd_state <= EVENT_CMD;
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command_ticks_reg <= out_command_ticks;
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command_hdr_reg <= out_command_hdr;
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command_data_reg <= out_command_data;
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end
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EVENT_CMD: begin // poking and peeking happens here!
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if (action || clear) cmd_state <= LOAD_CMD;
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end
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endcase //cmd_state
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end
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end
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//------------------------------------------------------------------
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//-- assign to settings bus interface
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//------------------------------------------------------------------
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reg strobe_reg;
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assign strobe = strobe_reg;
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assign data = command_data_reg;
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assign addr = command_hdr_reg[7:0];
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wire poke = command_hdr_reg[8];
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always @(posedge clock) begin
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if (reset || clear) strobe_reg <= 0;
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else strobe_reg <= action && poke;
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end
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//------------------------------------------------------------------
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//-- readback mux
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//------------------------------------------------------------------
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always @(posedge clock) begin
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case (out_command_hdr[3:0])
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0 : rb_data <= word00;
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1 : rb_data <= word01;
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2 : rb_data <= word02;
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3 : rb_data <= word03;
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4 : rb_data <= word04;
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5 : rb_data <= word05;
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6 : rb_data <= word06;
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7 : rb_data <= word07;
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8 : rb_data <= word08;
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9 : rb_data <= word09;
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10: rb_data <= word10;
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11: rb_data <= word11;
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12: rb_data <= word12;
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13: rb_data <= word13;
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14: rb_data <= word14;
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15: rb_data <= word15;
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endcase // case(addr_reg[3:0])
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end
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//------------------------------------------------------------------
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//-- Output state machine:
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//-- Read a command fifo entry, act on it, produce ack packet.
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//------------------------------------------------------------------
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localparam WRITE_PROT_HDR = 0;
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localparam WRITE_VRT_HDR = 1;
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localparam WRITE_VRT_SID = 2;
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localparam WRITE_RB_HDR = 3;
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localparam WRITE_RB_DATA = 4;
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//the state for the start of packet condition
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localparam WRITE_PKT_HDR = (PROT_HDR)? WRITE_PROT_HDR : WRITE_VRT_HDR;
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reg [2:0] out_state;
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assign out_valid = ~result_fifo_empty;
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assign result_fifo_read = out_data[33] && writing;
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always @(posedge clock) begin
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if (reset) begin
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out_state <= WRITE_PKT_HDR;
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end
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else if (writing && out_data[33]) begin
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out_state <= WRITE_PKT_HDR;
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end
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else if (writing) begin
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out_state <= out_state + 1;
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end
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end
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//------------------------------------------------------------------
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//-- assign to output fifo interface
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//------------------------------------------------------------------
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wire [31:0] prot_hdr;
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assign prot_hdr[15:0] = 16; //bytes in proceeding vita packet
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assign prot_hdr[16] = 1; //yes frame
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assign prot_hdr[18:17] = PROT_DEST;
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assign prot_hdr[31:19] = 0; //nothing
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reg [31:0] out_data_int;
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always @* begin
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case (out_state)
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WRITE_PROT_HDR: out_data_int <= prot_hdr;
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WRITE_VRT_HDR: out_data_int <= {12'b010100000000, out_result_hdr[19:16], 2'b0, prot_hdr[15:2]};
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WRITE_VRT_SID: out_data_int <= ACK_SID;
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WRITE_RB_HDR: out_data_int <= out_result_hdr;
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WRITE_RB_DATA: out_data_int <= out_result_data;
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default: out_data_int <= 0;
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endcase //state
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end
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assign out_data[35:34] = 2'b0;
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assign out_data[33] = (out_state == WRITE_RB_DATA);
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assign out_data[32] = (out_state == WRITE_PKT_HDR);
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assign out_data[31:0] = out_data_int;
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//------------------------------------------------------------------
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//-- debug outputs
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//------------------------------------------------------------------
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assign debug = {
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in_state, out_state, //8
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in_valid, in_ready, in_data[33:32], //4
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out_valid, out_ready, out_data[33:32], //4
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command_fifo_empty, command_fifo_full, //2
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command_fifo_read, command_fifo_write, //2
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addr, //8
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strobe_reg, strobe, poke, out_command_has_time //4
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};
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endmodule //settings_fifo_ctrl
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