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78 lines
2.4 KiB
Verilog
78 lines
2.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Automatic transmit/receive switching of control pins to daughterboards
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// Store everything in registers for now, but could use a RAM for more
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// complex state machines in the future
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module atr_controller
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(input clk_i, input rst_i,
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input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o,
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input we_i, input stb_i, input cyc_i, output reg ack_o,
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input run_rx, input run_tx,
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output [31:0] ctrl_lines);
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reg [3:0] state;
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reg [31:0] atr_ram [0:15]; // DP distributed RAM
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// WB Interface
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always @(posedge clk_i)
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if(we_i & stb_i & cyc_i)
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begin
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if(sel_i[3])
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atr_ram[adr_i[5:2]][31:24] <= dat_i[31:24];
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if(sel_i[2])
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atr_ram[adr_i[5:2]][23:16] <= dat_i[23:16];
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if(sel_i[1])
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atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
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if(sel_i[0])
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atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
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end // if (we_i & stb_i & cyc_i)
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// Removing readback allows ram to be synthesized as LUTs instead of regs
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//always @(posedge clk_i)
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// dat_o <= atr_ram[adr_i[5:2]];
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always
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dat_o <= 32'd0;
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always @(posedge clk_i)
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ack_o <= stb_i & cyc_i & ~ack_o;
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// Control side of DP RAM
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assign ctrl_lines = atr_ram[state];
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// Put a more complex state machine with time delays and multiple states here
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// if daughterboard requires more complex sequencing
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localparam ATR_IDLE = 4'd0;
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localparam ATR_TX = 4'd1;
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localparam ATR_RX = 4'd2;
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localparam ATR_FULL_DUPLEX = 4'd3;
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always @(posedge clk_i)
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if(rst_i)
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state <= ATR_IDLE;
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else
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case ({run_rx,run_tx})
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2'b00 : state <= ATR_IDLE;
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2'b01 : state <= ATR_TX;
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2'b10 : state <= ATR_RX;
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2'b11 : state <= ATR_FULL_DUPLEX;
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endcase // case({run_rx,run_tx})
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endmodule // atr_controller
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