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53 lines
1.3 KiB
Verilog
53 lines
1.3 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module clock_control_tb();
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clock_control clock_control
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(.reset(reset),
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.aux_clk(aux_clk),
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.clk_fpga(clk_fpga),
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.clk_en(clk_en),
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.clk_sel(clk_sel),
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.clk_func(clk_func),
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.clk_status(clk_status),
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.sen(sen),
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.sclk(sclk),
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.sdi(sdi),
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.sdo(sdo)
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);
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reg reset, aux_clk;
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wire [1:0] clk_sel, clk_en;
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initial reset = 1'b1;
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initial #1000 reset = 1'b0;
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initial aux_clk = 1'b0;
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always #10 aux_clk = ~aux_clk;
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initial $dumpfile("clock_control_tb.vcd");
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initial $dumpvars(0,clock_control_tb);
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initial #10000 $finish;
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endmodule // clock_control_tb
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