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https://github.com/fairwaves/UHD-Fairwaves.git
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89 lines
3.0 KiB
Verilog
89 lines
3.0 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module quad_uart
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#(parameter TXDEPTH = 1,
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parameter RXDEPTH = 1)
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(input clk_i, input rst_i,
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input we_i, input stb_i, input cyc_i, output reg ack_o,
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input [4:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
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output [3:0] rx_int_o, output [3:0] tx_int_o,
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output [3:0] tx_o, input [3:0] rx_i, output [3:0] baud_o
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);
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// Register Map
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localparam SUART_CLKDIV = 0;
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localparam SUART_TXLEVEL = 1;
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localparam SUART_RXLEVEL = 2;
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localparam SUART_TXCHAR = 3;
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localparam SUART_RXCHAR = 4;
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wire wb_acc = cyc_i & stb_i; // WISHBONE access
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wire wb_wr = wb_acc & we_i; // WISHBONE write access
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reg [15:0] clkdiv[0:3];
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wire [7:0] rx_char[0:3];
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wire [3:0] tx_fifo_full, rx_fifo_empty;
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wire [7:0] tx_fifo_level[0:3], rx_fifo_level[0:3];
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always @(posedge clk_i)
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if (rst_i)
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ack_o <= 1'b0;
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else
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ack_o <= wb_acc & ~ack_o;
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integer i;
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always @(posedge clk_i)
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if (rst_i)
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for(i=0;i<4;i=i+1)
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clkdiv[i] <= 0;
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else if (wb_wr)
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case(adr_i[2:0])
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SUART_CLKDIV : clkdiv[adr_i[4:3]] <= dat_i[15:0];
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endcase // case(adr_i)
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always @(posedge clk_i)
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case (adr_i[2:0])
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SUART_TXLEVEL : dat_o <= tx_fifo_level[adr_i[4:3]];
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SUART_RXLEVEL : dat_o <= rx_fifo_level[adr_i[4:3]];
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SUART_RXCHAR : dat_o <= rx_char[adr_i[4:3]];
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endcase // case(adr_i)
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genvar j;
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generate
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for(j=0;j<4;j=j+1)
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begin : gen_uarts
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simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx
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(.clk(clk_i),.rst(rst_i),
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.fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i[2:0] == SUART_TXCHAR) && (adr_i[4:3]==j)),
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.fifo_level(tx_fifo_level[j]),.fifo_full(tx_fifo_full[j]),
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.clkdiv(clkdiv[j]),.baudclk(baud_o[j]),.tx(tx_o[j]));
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simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx
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(.clk(clk_i),.rst(rst_i),
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.fifo_out(rx_char[j]),.fifo_read(ack_o && ~wb_wr && (adr_i[2:0] == SUART_RXCHAR) && (adr_i[4:3]==j)),
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.fifo_level(rx_fifo_level[j]),.fifo_empty(rx_fifo_empty[j]),
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.clkdiv(clkdiv[j]),.rx(rx_i[j]));
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end // block: gen_uarts
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endgenerate
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assign tx_int_o = ~tx_fifo_full; // Interrupt for those that have space
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assign rx_int_o = ~rx_fifo_empty; // Interrupt for those that have data
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endmodule // quad_uart
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