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0a3dd778d0
Looks like icap clk from the pll is shared with the frontend clock. So instead I opted to divide the icap clk down inside s6_icap_wb.v. The image checked in reset reliably after many trials, which is a good sign that this may be an acceptable fix.
71 lines
2.1 KiB
Verilog
71 lines
2.1 KiB
Verilog
//
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// Copyright 2013 Andrew Karpenkov, Fairwaves LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//ATTENTION!! Maximum ICAP clock in Spartan 6 is 20 MHz!!!
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module s6_icap_wb
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(input clk, input clk_icap, input reset,
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input cyc_i, input stb_i, input we_i, output reg ack_o,
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input [31:0] dat_i, output reg[31:0] dat_o);//, output [31:0] debug_out);
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reg slow_clk_icap;
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always @(posedge clk_icap) slow_clk_icap <= ~slow_clk_icap;
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wire BUSY, CE, WRITE;
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wire[31:0] s1_dat_i;
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reg[31:0] s_dat_o;
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wire[31:0] s1_dat_o;
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assign s1_dat_o[31:16] = 16'd0;
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wire full, empty;
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fifo_xlnx_16x40_2clk icap_fifo
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(.rst(reset),
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.wr_clk(clk), .din(dat_i), .wr_en(we_i & stb_i & ~ack_o & ~full), .full(full),
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.rd_clk(slow_clk_icap), .dout(s1_dat_i), .rd_en(~empty), .empty(empty));
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assign WRITE = empty;
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assign CE = empty;
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ICAP_SPARTAN6 ICAP_SPARTAN6_inst
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(.BUSY(BUSY), // Busy output
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.O(s1_dat_o[15:0]), // 16-bit data output
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.CE(CE), // Clock enable input
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.CLK(slow_clk_icap), // Clock input
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.I(s1_dat_i[15:0]), // 16-bit data input
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.WRITE(WRITE) // Write input
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);
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//cross back to Wishbone clock domain
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always @(posedge clk)
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if (reset)
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begin
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s_dat_o <= 32'd0;
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dat_o <= 32'd0;
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ack_o <= 1'b0;
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end
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else
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begin
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s_dat_o <= s1_dat_o;
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dat_o[15:0] <= s_dat_o[15:0];
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ack_o <= stb_i & ~ack_o;
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end
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endmodule // s6_icap_wb
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