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43 lines
1.2 KiB
Verilog
43 lines
1.2 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module setting_reg
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#(parameter my_addr = 0,
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parameter width = 32,
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parameter at_reset=32'd0)
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(input clk, input rst, input strobe, input wire [7:0] addr,
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input wire [31:0] in, output reg [width-1:0] out, output reg changed);
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always @(posedge clk)
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if(rst)
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begin
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out <= at_reset;
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changed <= 1'b0;
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end
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else
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if(strobe & (my_addr==addr))
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begin
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out <= in;
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changed <= 1'b1;
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end
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else
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changed <= 1'b0;
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endmodule // setting_reg
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