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39 lines
1.5 KiB
Verilog
39 lines
1.5 KiB
Verilog
//
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// Copyright 2011-2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// This module takes the settings bus on one clock domain and crosses it over to another domain
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// Typically it will be used with the input settings bus on the wishbone clock, and either
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// the system or dsp clock on the output side
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module settings_bus_crossclock
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#(parameter FLOW_CTRL=0)
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(input clk_i, input rst_i, input set_stb_i, input [7:0] set_addr_i, input [31:0] set_data_i,
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input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o, input blocked);
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wire full, empty;
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fifo_xlnx_16x40_2clk settings_fifo
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(.rst(rst_i),
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.wr_clk(clk_i), .din({set_addr_i,set_data_i}), .wr_en(set_stb_i & ~full), .full(full),
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.rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(set_stb_o), .empty(empty));
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assign set_stb_o = ~empty & (~blocked | ~FLOW_CTRL);
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endmodule // settings_bus_crossclock
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