mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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82 lines
2.2 KiB
Verilog
82 lines
2.2 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module simple_uart_rx
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#(parameter DEPTH=0)
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(input clk, input rst,
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output [7:0] fifo_out, input fifo_read, output [7:0] fifo_level, output fifo_empty,
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input [15:0] clkdiv, input rx);
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reg rx_d1, rx_d2;
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always @(posedge clk)
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if(rst)
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{rx_d2,rx_d1} <= 0;
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else
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{rx_d2,rx_d1} <= {rx_d1,rx};
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reg [15:0] baud_ctr;
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reg [3:0] bit_ctr;
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reg [7:0] sr;
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wire neg_trans = rx_d2 & ~rx_d1;
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wire shift_now = baud_ctr == (clkdiv>>1);
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wire stop_now = (bit_ctr == 10) && shift_now;
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wire go_now = (bit_ctr == 0) && neg_trans;
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always @(posedge clk)
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if(rst)
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sr <= 0;
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else if(shift_now)
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sr <= {rx_d2,sr[7:1]};
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always @(posedge clk)
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if(rst)
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baud_ctr <= 0;
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else
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if(go_now)
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baud_ctr <= 1;
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else if(stop_now)
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baud_ctr <= 0;
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else if(baud_ctr >= clkdiv)
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baud_ctr <= 1;
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else if(baud_ctr != 0)
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baud_ctr <= baud_ctr + 1;
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always @(posedge clk)
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if(rst)
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bit_ctr <= 0;
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else
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if(go_now)
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bit_ctr <= 1;
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else if(stop_now)
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bit_ctr <= 0;
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else if(baud_ctr == clkdiv)
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bit_ctr <= bit_ctr + 1;
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wire full;
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wire write = ~full & rx_d2 & stop_now;
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medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo
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(.clk(clk),.rst(rst),
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.datain(sr),.write(write),.full(full),
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.dataout(fifo_out),.read(fifo_read),.empty(fifo_empty),
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.clear(0),.space(),.occupied(fifo_level) );
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endmodule // simple_uart_rx
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