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UHD-Fairwaves/fpga/extramfifo/coregen.cgp
2014-04-07 17:34:55 -07:00

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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx75
SET devicefamily = spartan6
SET flowvendor = Other
SET package = fgg484
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false