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https://github.com/fairwaves/UHD-Fairwaves.git
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66 lines
1.8 KiB
Verilog
66 lines
1.8 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module adc_model
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(input clk, input rst,
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output [13:0] adc_a,
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output adc_ovf_a,
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input adc_on_a,
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input adc_oe_a,
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output [13:0] adc_b,
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output adc_ovf_b,
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input adc_on_b,
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input adc_oe_b
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);
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math_real math ( ) ;
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reg [13:0] adc_a_int = 0;
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reg [13:0] adc_b_int = 0;
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assign adc_a = adc_oe_a ? adc_a_int : 14'bz;
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assign adc_ovf_a = adc_oe_a ? 1'b0 : 1'bz;
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assign adc_b = adc_oe_b ? adc_b_int : 14'bz;
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assign adc_ovf_b = adc_oe_b ? 1'b0 : 1'bz;
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real phase = 0;
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real freq = 330000/100000000;
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real scale = 8190; // math.pow(2,13)-2;
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always @(posedge clk)
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if(rst)
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begin
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adc_a_int <= 0;
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adc_b_int <= 0;
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end
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else
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begin
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if(adc_on_a)
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//adc_a_int <= $rtoi(math.round(math.sin(phase*math.MATH_2_PI)*scale)) ;
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adc_a_int <= adc_a_int + 3;
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if(adc_on_b)
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adc_b_int <= adc_b_int - 7;
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//adc_b_int <= $rtoi(math.round(math.cos(phase*math.MATH_2_PI)*scale)) ;
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if(phase > 1)
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phase <= phase + freq - 1;
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else
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phase <= phase + freq;
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end
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endmodule // adc_model
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