mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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66 lines
1.6 KiB
Verilog
66 lines
1.6 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Simple printout of characters from the UART
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// Only does 8N1, requires the baud clock
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module uart_rx (input baudclk, input rxd);
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reg [8:0] sr = 9'b0;
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reg [3:0] baud_ctr = 4'b0;
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/*
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wire byteclk = baud_ctr[3];
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reg rxd_d1 = 0;
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always @(posedge baudclk)
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rxd_d1 <= rxd;
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always @(posedge baudclk)
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if(rxd_d1 != rxd)
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baud_ctr <= 0;
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else
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baud_ctr <= baud_ctr + 1;
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*/
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wire byteclk = baudclk;
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always @(posedge byteclk)
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sr <= { rxd, sr[8:1] };
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reg [3:0] state = 0;
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always @(posedge byteclk)
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case(state)
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0 :
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if(~sr[8] & sr[7]) // found start bit
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state <= 1;
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1, 2, 3, 4, 5, 6, 7, 8 :
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state <= state + 1;
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9 :
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begin
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state <= 0;
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$write("%c",sr[7:0]);
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if(~sr[8])
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$display("Error, no stop bit\n");
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end
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default :
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state <= 0;
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endcase // case(state)
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endmodule // uart_rx
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