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https://github.com/fairwaves/UHD-Fairwaves.git
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80 lines
2.2 KiB
Verilog
80 lines
2.2 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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`define DSP_CORE_RX_BASE 160
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module dummy_rx
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(input clk, input rst,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input [13:0] adc_a, input adc_ovf_a,
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input [13:0] adc_b, input adc_ovf_b,
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output [31:0] sample,
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input run,
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output strobe
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);
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wire [15:0] scale_i, scale_q;
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wire [31:0] phase_inc;
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reg [31:0] phase;
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wire [23:0] i_decim, q_decim;
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wire [7:0] decim_rate;
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setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(phase_inc),.changed());
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setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({scale_i,scale_q}),.changed());
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setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(decim_rate),.changed());
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strobe_gen strobe_gen(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate),
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.strobe_in(1),.strobe(strobe) );
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reg [15:0] i_out, q_out;
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assign sample = {i_out,q_out};
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always @(posedge clk)
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if(rst)
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i_out <= 0;
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else if(~run)
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i_out <= 0;
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else if(strobe)
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i_out <= i_out + 1;
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reg run_d1;
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always @(posedge clk)
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if(rst)
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run_d1 <= 0;
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else
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run_d1 <= run;
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always @(posedge clk)
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if(rst)
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q_out <= 0;
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else if (run & ~run_d1)
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q_out <= q_out + 1;
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endmodule // ddc_chain
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