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https://github.com/fairwaves/UHD-Fairwaves.git
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110 lines
4.6 KiB
Verilog
110 lines
4.6 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module udp_wrapper
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#(parameter BASE=0)
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(input clk, input reset, input clear,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o,
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output [18:0] tx_f19_data, output tx_f19_src_rdy_o, input tx_f19_dst_rdy_i,
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output [35:0] rx_f36_data, output rx_f36_src_rdy_o, input rx_f36_dst_rdy_i,
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input [35:0] tx_f36_data, input tx_f36_src_rdy_i, output tx_f36_dst_rdy_o,
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output [31:0] debug
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);
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wire tx_int1_src_rdy, tx_int1_dst_rdy;
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wire [18:0] tx_int1_data;
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wire tx_int2_src_rdy, tx_int2_dst_rdy;
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wire [18:0] tx_int2_data;
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wire [31:0] debug_state;
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// TX side
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fifo36_to_fifo19 fifo36_to_fifo19
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(.clk(clk), .reset(reset), .clear(clear),
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.f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_i), .f36_dst_rdy_o(tx_f36_dst_rdy_o),
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.f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), .f19_dst_rdy_i(tx_int1_dst_rdy) );
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fifo_short #(.WIDTH(19)) shortfifo19_a
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(.clk(clk), .reset(reset), .clear(clear),
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.datain(tx_int1_data), .src_rdy_i(tx_int1_src_rdy), .dst_rdy_o(tx_int1_dst_rdy),
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.dataout(tx_int2_data), .src_rdy_o(tx_int2_src_rdy), .dst_rdy_i(tx_int2_dst_rdy),
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.space(), .occupied() );
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prot_eng_tx #(.BASE(BASE)) prot_eng_tx
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(.clk(clk), .reset(reset), .clear(clear),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.datain(tx_int2_data), .src_rdy_i(tx_int2_src_rdy), .dst_rdy_o(tx_int2_dst_rdy),
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.dataout(tx_f19_data), .src_rdy_o(tx_f19_src_rdy_o), .dst_rdy_i(tx_f19_dst_rdy_i) );
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// RX side
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wire rx_int1_src_rdy, rx_int1_dst_rdy;
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wire [18:0] rx_int1_data;
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wire rx_int2_src_rdy, rx_int2_dst_rdy;
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wire [18:0] rx_int2_data;
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//wire rx_int3_src_rdy, rx_int3_dst_rdy;
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//wire [35:0] rx_int3_data;
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`ifdef USE_PROT_ENG
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prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx
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(.clk(clk), .reset(reset), .clear(clear),
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.datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o),
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.dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) );
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`else
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fifo19_rxrealign fifo19_rxrealign
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(.clk(clk), .reset(reset), .clear(clear),
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.datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o),
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.dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) );
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`endif // !`ifdef USE_PROT_ENG
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fifo_short #(.WIDTH(19)) shortfifo19_b
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(.clk(clk), .reset(reset), .clear(clear),
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.datain(rx_int1_data), .src_rdy_i(rx_int1_src_rdy), .dst_rdy_o(rx_int1_dst_rdy),
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.dataout(rx_int2_data), .src_rdy_o(rx_int2_src_rdy), .dst_rdy_i(rx_int2_dst_rdy),
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.space(), .occupied() );
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fifo19_to_fifo36 fifo19_to_fifo36
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(.clk(clk), .reset(reset), .clear(clear),
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.f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy),
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.f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy_o), .f36_dst_rdy_i(rx_f36_dst_rdy_i),
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.debug(debug_state));
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/*
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fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo
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(.clk(clk), .reset(reset), .clear(clear),
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.datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy),
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.dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i),
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.space(), .occupied() );
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*/
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/*
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assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i },
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{ 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy},
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{ rx_int3_data[35:32], rx_f36_data[35:32] },
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{ debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } };
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*/
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assign debug = { { 3'd0, tx_int1_src_rdy, tx_int1_dst_rdy, tx_int1_data[18:16] },
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{ 3'd0, tx_int2_src_rdy, tx_int2_dst_rdy, tx_int2_data[18:16] },
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{ tx_int2_data[15:8] },
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{ tx_int2_data[7:0] } };
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endmodule // udp_wrapper
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