Files
UHD-Fairwaves/fpga
Josh Blum 0a3dd778d0 umtrx: slow down icap clock, this image resets reliably
Looks like icap clk from the pll is shared with the frontend clock.
So instead I opted to divide the icap clk down inside s6_icap_wb.v.
The image checked in reset reliably after many trials,
which is a good sign that this may be an acceptable fix.
2015-04-01 00:45:00 -07:00
..
2015-03-17 12:05:23 -07:00