mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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67 lines
1.9 KiB
Verilog
67 lines
1.9 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Simple 32-bit Wishbone compatible slave output port
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// with 8-bit granularity, modeled after the one in the spec
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// Allows for readback
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// Assumes a 32-bit wishbone bus
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// Lowest order bits get sel[0]
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//
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module wb_output_pins32
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(wb_rst_i, wb_clk_i, wb_dat_i, wb_dat_o,
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wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i,
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port_output);
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input wb_rst_i;
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input wb_clk_i;
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input wire [31:0] wb_dat_i;
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output wire [31:0] wb_dat_o;
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input wb_we_i;
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input wire [3:0] wb_sel_i;
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input wb_stb_i;
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output wb_ack_o;
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input wb_cyc_i;
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output wire [31:0] port_output;
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reg [31:0] internal_reg;
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always @(posedge wb_clk_i)
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if(wb_rst_i)
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internal_reg <= #1 32'b0;
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else
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begin
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if(wb_stb_i & wb_we_i & wb_sel_i[0])
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internal_reg[7:0] <= #1 wb_dat_i[7:0];
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if(wb_stb_i & wb_we_i & wb_sel_i[1])
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internal_reg[15:8] <= #1 wb_dat_i[15:8];
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if(wb_stb_i & wb_we_i & wb_sel_i[2])
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internal_reg[23:16] <= #1 wb_dat_i[23:16];
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if(wb_stb_i & wb_we_i & wb_sel_i[3])
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internal_reg[31:24] <= #1 wb_dat_i[31:24];
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end // else: !if(wb_rst_i)
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assign wb_dat_o = internal_reg;
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assign port_output = internal_reg;
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assign wb_ack_o = wb_stb_i;
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endmodule // wb_output_pins32
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