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https://github.com/fairwaves/UHD-Fairwaves.git
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67 lines
2.2 KiB
Verilog
67 lines
2.2 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Control DSP pipeline with 1 cycle per stage. Minimum 2 stages or this won't work
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module pipectrl
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#(parameter STAGES = 2,
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parameter TAGWIDTH = 1)
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(input clk,
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input reset,
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input src_rdy_i,
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output dst_rdy_o,
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output src_rdy_o,
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input dst_rdy_i,
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output [STAGES-1:0] strobes,
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output [STAGES-1:0] valids,
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input [TAGWIDTH-1:0] tag_i,
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output [TAGWIDTH-1:0] tag_o);
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wire new_input = src_rdy_i & dst_rdy_o;
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wire new_output = src_rdy_o & dst_rdy_i;
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wire [TAGWIDTH-1:0] tags [STAGES-1:0];
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assign dst_rdy_o = ~valids[0] | strobes[1];
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pipestage #(.TAGWIDTH(TAGWIDTH)) head
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(.clk(clk),.reset(reset), .stb_in(strobes[0]), .stb_out(strobes[1]),.valid(valids[0]),
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.tag_in(tag_i), .tag_out(tags[0]));
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assign strobes[0] = src_rdy_i & (~valids[0] | strobes[1]);
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genvar i;
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generate
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for(i = 1; i < STAGES - 1; i = i + 1)
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begin : gen_stages
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pipestage #(.TAGWIDTH(TAGWIDTH)) pipestage
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(.clk(clk),.reset(reset), .stb_in(strobes[i]),.stb_out(strobes[i+1]),.valid(valids[i]),
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.tag_in(tags[i-1]),.tag_out(tags[i]));
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assign strobes[i] = valids[i-1] & (~valids[i] | strobes[i+1]);
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end
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endgenerate
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pipestage #(.TAGWIDTH(TAGWIDTH)) tail
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(.clk(clk),.reset(reset), .stb_in(strobes[STAGES-1]), .stb_out(dst_rdy_i),.valid(valids[STAGES-1]),
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.tag_in(tags[STAGES-2]), .tag_out(tags[STAGES-1]));
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assign strobes[STAGES-1] = valids[STAGES-2] & (~valids[STAGES-1] | new_output);
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assign src_rdy_o = valids[STAGES-1];
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assign tag_o = tags[STAGES-1];
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endmodule // pipectrl
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