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45 lines
1.4 KiB
Verilog
45 lines
1.4 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2008 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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// Rounding "macro"
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// Keeps the topmost bits, does proper 2s comp rounding (round-to-zero)
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module round_reg
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#(parameter bits_in=0,
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parameter bits_out=0)
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(input clk,
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input [bits_in-1:0] in,
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output reg [bits_out-1:0] out,
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output reg [bits_in-bits_out:0] err);
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wire [bits_out-1:0] temp;
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wire [bits_in-bits_out:0] err_temp;
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round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp), .err(err_temp));
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always @(posedge clk)
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out <= temp;
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always @(posedge clk)
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err <= err_temp;
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endmodule // round_reg
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