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37 lines
1.0 KiB
Makefile
37 lines
1.0 KiB
Makefile
#
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# Copyright 2010 Ettus Research LLC
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#
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##################################################
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# Open Cores Sources
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##################################################
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OPENCORES_SRCS = $(abspath $(addprefix $(BASE_DIR)/../opencores/, \
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8b10b/decode_8b10b.v \
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8b10b/encode_8b10b.v \
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aemb/rtl/verilog/aeMB_bpcu.v \
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aemb/rtl/verilog/aeMB_core_BE.v \
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aemb/rtl/verilog/aeMB_ctrl.v \
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aemb/rtl/verilog/aeMB_edk32.v \
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aemb/rtl/verilog/aeMB_ibuf.v \
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aemb/rtl/verilog/aeMB_regf.v \
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aemb/rtl/verilog/aeMB_xecu.v \
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i2c/rtl/verilog/i2c_master_bit_ctrl.v \
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i2c/rtl/verilog/i2c_master_byte_ctrl.v \
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i2c/rtl/verilog/i2c_master_defines.v \
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i2c/rtl/verilog/i2c_master_top.v \
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i2c/rtl/verilog/timescale.v \
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spi/rtl/verilog/spi_clgen.v \
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spi/rtl/verilog/spi_defines.v \
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spi/rtl/verilog/spi_shift.v \
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spi/rtl/verilog/spi_top.v \
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spi/rtl/verilog/spi_top16.v \
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zpu/zpu_top_pkg.vhd \
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zpu/zpu_wb_top.vhd \
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zpu/wishbone/wishbone_pkg.vhd \
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zpu/wishbone/zpu_system.vhd \
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zpu/wishbone/zpu_wb_bridge.vhd \
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zpu/core/zpu_config.vhd \
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zpu/core/zpu_core.vhd \
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zpu/core/zpupkg.vhd \
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))
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