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			63 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			Python
		
	
	
		
			Executable File
		
	
	
	
	
			
		
		
	
	
			63 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			Python
		
	
	
		
			Executable File
		
	
	
	
	
#!/usr/bin/env python
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#
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# Copyright 2010 Ettus Research LLC
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program.  If not, see <http://www.gnu.org/licenses/>.
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#
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# Description:
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# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf.
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# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes
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import sys
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import re
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if __name__=='__main__':
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  if len(sys.argv) == 2:
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    print "Usage: %s <top level Verilog file> <pin definition UCF>"
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    sys.exit(-1)
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  verilog_filename = sys.argv[1]
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  ucf_filename = sys.argv[2]
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  verilog_file = open(verilog_filename, 'r')
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  ucf_file = open(ucf_filename, 'r')
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  verilog_iolist = list()
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  ucf_iolist = list()
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  #read in all input, inout, and output declarations and compile a list
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  for line in verilog_file:
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    for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]):
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      verilog_iolist.append(match)
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  for line in ucf_file:
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      m = re.search(r"""NET "(\w+).*" """, line.split("#")[0])
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      if m is not None:
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        ucf_iolist.append(m.group(1))
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  #now find corresponding matches and error when you don't find one
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  #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem
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  err = False
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  for item in verilog_iolist:
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    if item not in ucf_iolist:
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      print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item
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      err = True
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  if err:
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    sys.exit(-1)
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  print "No errors found."
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  sys.exit(0)
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