mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
synced 2025-11-02 13:03:13 +00:00
342 lines
9.3 KiB
Verilog
342 lines
9.3 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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module single_u2_sim();
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// Misc, debug
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wire [7:0] leds;
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wire [31:0] debug;
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wire [1:0] debug_clk;
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// Expansion
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wire exp_pps_in;
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wire exp_pps_out;
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// GMII
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// GMII-CTRL
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wire GMII_COL;
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wire GMII_CRS;
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// GMII-TX
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wire [7:0] GMII_TXD;
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wire GMII_TX_EN;
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wire GMII_TX_ER;
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wire GMII_GTX_CLK;
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wire GMII_TX_CLK; // 100mbps clk
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// GMII-RX
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wire [7:0] GMII_RXD;
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wire GMII_RX_CLK;
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wire GMII_RX_DV;
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wire GMII_RX_ER;
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// GMII-Management
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wire MDIO;
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wire MDC;
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wire PHY_INTn; // open drain
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wire PHY_RESETn;
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wire PHY_CLK; // possibly use on-board osc
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// RAM
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wire [17:0] RAM_D;
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wire [18:0] RAM_A;
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wire RAM_CE1n;
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wire RAM_CENn;
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wire RAM_CLK;
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wire RAM_WEn;
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wire RAM_OEn;
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wire RAM_LDn;
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// SERDES
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wire ser_enable;
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wire ser_prbsen;
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wire ser_loopen;
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wire ser_rx_en;
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wire ser_tx_clk;
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wire [15:0] ser_t;
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wire ser_tklsb;
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wire ser_tkmsb;
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wire ser_rx_clk;
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wire [15:0] ser_r;
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wire ser_rklsb;
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wire ser_rkmsb;
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// CPLD interface
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wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done;
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// ADC
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wire [13:0] adc_a;
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wire adc_ovf_a;
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wire adc_on_a, adc_oe_a;
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wire [13:0] adc_b;
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wire adc_ovf_b;
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wire adc_on_b, adc_oe_b;
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// DAC
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wire [15:0] dac_a;
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wire [15:0] dac_b;
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// I2C
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wire SCL;
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wire SDA;
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// Clock Gen Control
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wire [1:0] clk_en;
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wire [1:0] clk_sel;
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wire clk_func; // FIXME is an input to control the 9510
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wire clk_status;
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// Clocks
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reg clk_fpga;
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reg clk_to_mac;
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wire pps_in;
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// Generic SPI
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wire sclk, mosi, miso;
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wire sen_clk;
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wire sen_dac;
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wire sen_tx_db;
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wire sen_tx_adc;
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wire sen_tx_dac;
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wire sen_rx_db;
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wire sen_rx_adc;
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wire sen_rx_dac;
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// GPIO to DBoards
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wire [15:0] io_tx;
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wire [15:0] io_rx;
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wire wb_clk;
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wire start, clock_ready;
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reg aux_clk;
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initial aux_clk= 1'b0;
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always #6 aux_clk = ~aux_clk;
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initial clk_fpga = 1'bx;
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initial #3007 clk_fpga = 1'b0;
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always #5 clk_fpga = ~clk_fpga;
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initial clk_to_mac = 0;
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always #4 clk_to_mac = ~clk_to_mac;
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wire div_clk, dsp_clk;
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reg [7:0] div_ctr = 0;
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assign dsp_clk = clock_ready ? clk_fpga : aux_clk;
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assign wb_clk = div_clk;
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`define CLK_DIV_2 1
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//`define CLK_DIV_3
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`ifdef CLK_DIV_2
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localparam clock_divider = 4'd2;
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always @(posedge dsp_clk)
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div_ctr <= div_ctr + 1;
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assign div_clk = div_ctr[0];
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`endif
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`ifdef CLK_DIV_3
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localparam clock_divider = 2;
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always @(posedge dsp_clk or negedge dsp_clk)
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if(div_ctr == 5)
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div_ctr <= 0;
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else
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div_ctr <= div_ctr + 1;
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assign div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2));
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`endif
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initial
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$monitor($time, ,clock_ready);
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always #1000000 $monitor("Time in ns ",$time);
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initial begin
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@(negedge cpld_done);
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@(posedge cpld_done);
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$dumpfile("single_u2_sim.lxt");
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$dumpvars(0,single_u2_sim);
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end
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initial #10000000 $finish;
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cpld_model
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cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done),
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.dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached));
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serdes_model serdes_model
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(.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t),
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.ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r),
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.even(0),.error(0) );
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adc_model adc_model
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(.clk(dsp_clk),.rst(0),
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.adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a),
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.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) );
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wire [2:0] speed;
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phy_sim phy_model
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(.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK),
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.Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD),
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.Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD),
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.Crs(GMII_CRS), .Col(GMII_COL),
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.Speed(speed), .Done(0) );
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pullup p3(MDIO);
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miim_model miim_model
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(.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK),
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.phy_intn_o(PHY_INTn),.speed_o(speed) );
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xlnx_glbl glbl (.GSR(),.GTS());
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wire RAM_MODE = 1'b0;
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cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A),
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.bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn),
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.ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0),
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.oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) );
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M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0),
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.SDA(SDA),.SCL(SCL),.RESET(0));
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wire scl_pad_i, scl_pad_o, scl_pad_oen_o;
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wire sda_pad_i, sda_pad_o, sda_pad_oen_o;
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pullup p1(SCL);
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pullup p2(SDA);
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assign scl_pad_i = SCL;
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assign sda_pad_i = SDA;
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assign SCL = scl_pad_oen_o ? 1'bz : scl_pad_o;
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assign SDA = sda_pad_oen_o ? 1'bz : sda_pad_o;
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// printf output
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wire uart_baud_o, uart_tx_o, uart_rx_i;
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assign uart_rx_i = 1'b1;
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uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o));
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// End the simulation
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always @(posedge wb_clk)
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if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0))
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begin
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$display($time, "Finish called.",);
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$finish;
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end
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u2_core #(.RAM_SIZE(32768))
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u2_core(.dsp_clk (dsp_clk),
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.wb_clk (wb_clk),
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.clock_ready (clock_ready),
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.clk_to_mac (clk_to_mac),
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.pps_in (pps_in),
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.leds (leds),
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.debug (debug[31:0]),
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.debug_clk (debug_clk[1:0]),
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.exp_pps_in (exp_pps_in),
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.exp_pps_out (exp_pps_out),
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.GMII_COL (GMII_COL),
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.GMII_CRS (GMII_CRS),
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.GMII_TXD (GMII_TXD[7:0]),
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.GMII_TX_EN (GMII_TX_EN),
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.GMII_TX_ER (GMII_TX_ER),
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.GMII_GTX_CLK (GMII_GTX_CLK),
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.GMII_TX_CLK (GMII_TX_CLK),
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.GMII_RXD (GMII_RXD[7:0]),
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.GMII_RX_CLK (GMII_RX_CLK),
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.GMII_RX_DV (GMII_RX_DV),
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.GMII_RX_ER (GMII_RX_ER),
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.MDIO (MDIO),
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.MDC (MDC),
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.PHY_INTn (PHY_INTn),
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.PHY_RESETn (PHY_RESETn),
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.ser_enable (ser_enable),
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.ser_prbsen (ser_prbsen),
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.ser_loopen (ser_loopen),
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.ser_rx_en (ser_rx_en),
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.ser_tx_clk (ser_tx_clk),
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.ser_t (ser_t[15:0]),
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.ser_tklsb (ser_tklsb),
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.ser_tkmsb (ser_tkmsb),
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.ser_rx_clk (ser_rx_clk),
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.ser_r (ser_r[15:0]),
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.ser_rklsb (ser_rklsb),
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.ser_rkmsb (ser_rkmsb),
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.cpld_start (cpld_start),
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.cpld_mode (cpld_mode),
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.cpld_done (cpld_done),
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.cpld_din (cpld_din),
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.cpld_clk (cpld_clk),
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.cpld_detached (cpld_detached),
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.cpld_init_b (1),
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.por (0),
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.adc_a (adc_a[13:0]),
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.adc_ovf_a (adc_ovf_a),
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.adc_on_a (adc_on_a),
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.adc_oe_a (adc_oe_a),
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.adc_b (adc_b[13:0]),
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.adc_ovf_b (adc_ovf_b),
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.adc_on_b (adc_on_b),
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.adc_oe_b (adc_oe_b),
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.dac_a (dac_a[15:0]),
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.dac_b (dac_b[15:0]),
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.scl_pad_i (scl_pad_i),
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.scl_pad_o (scl_pad_o),
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.scl_pad_oen_o (scl_pad_oen_o),
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.sda_pad_i (sda_pad_i),
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.sda_pad_o (sda_pad_o),
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.sda_pad_oen_o (sda_pad_oen_o),
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.clk_en (clk_en[1:0]),
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.clk_sel (clk_sel[1:0]),
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.clk_func (clk_func),
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.clk_status (clk_status),
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.sclk (sclk),
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.mosi (mosi),
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.miso (miso),
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.sen_clk (sen_clk),
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.sen_dac (sen_dac),
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.sen_tx_db (sen_tx_db),
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.sen_tx_adc (sen_tx_adc),
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.sen_tx_dac (sen_tx_dac),
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.sen_rx_db (sen_rx_db),
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.sen_rx_adc (sen_rx_adc),
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.sen_rx_dac (sen_rx_dac),
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.io_tx (io_tx[15:0]),
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.io_rx (io_rx[15:0]),
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.RAM_D (RAM_D),
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.RAM_A (RAM_A),
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.RAM_CE1n (RAM_CE1n),
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.RAM_CENn (RAM_CENn),
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.RAM_CLK (RAM_CLK),
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.RAM_WEn (RAM_WEn),
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.RAM_OEn (RAM_OEn),
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.RAM_LDn (RAM_LDn),
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.uart_tx_o (uart_tx_o),
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.uart_rx_i (uart_rx_i),
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.uart_baud_o (uart_baud_o),
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.sim_mode (1'b1),
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.clock_divider (clock_divider)
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);
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endmodule // single_u2_sim
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