Files
openbts-2.8/TransceiverRAD1/fpga/megacells/add32_inst.v
hsamra 9704fa28e7 FPGA source code.
git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@3457 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2012-04-15 05:11:26 +00:00

6 lines
93 B
Verilog

add32 add32_inst (
.dataa ( dataa_sig ),
.datab ( datab_sig ),
.result ( result_sig )
);