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uhd: Update B200 timing compensation for UHD 3.9.0

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Version change to UHD 3.9.0 includes FIR filter changes in the FPGA that
alter group delay and consequently offset uplink/downlink slot alignment.
Only B200 is affected. Add compile time version check for new timing
values.

Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
This commit is contained in:
Tom Tsou
2015-04-14 17:58:29 -07:00
committed by Michael Iedema
parent 25363b4e5d
commit 42cc2d123d
2 changed files with 35 additions and 17 deletions
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7
configure.ac
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@@ -88,8 +88,11 @@ AS_IF([test "x$with_usrp1" = "xyes"], [
])
AS_IF([test "x$with_uhd" = "xyes"],[
PKG_CHECK_MODULES(UHD, uhd >= 003.005.004)
AC_DEFINE(USE_UHD, 1, Define to 1 if using UHD)
PKG_CHECK_MODULES(UHD, uhd >= 003.009,
[AC_DEFINE(USE_UHD_3_9, 1, UHD version 3.9.0 or higher)],
[PKG_CHECK_MODULES(UHD, uhd >= 003.005.004)]
)
AC_DEFINE(USE_UHD, 1, Other UHD versions)
AX_EXT
])