mirror of
https://github.com/RangeNetworks/openbts.git
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Putting the actual OpenBTS P2.8 source code into the public SVN branch.
git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2242 19bc5d8c-e614-43d4-8b26-e1612bc8e597
This commit is contained in:
David Burgess
318
TransceiverRAD1/rnrad1Rx.cpp
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318
TransceiverRAD1/rnrad1Rx.cpp
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/*
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* Copyright 2008, 2009 Free Software Foundation, Inc.
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*
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*
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* This software is distributed under the terms of the GNU Affero Public License.
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* See the COPYING file in the main directory for details.
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*
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* This use of this software may be subject to additional restrictions.
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* See the LEGAL file in the main directory for details.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU Affero General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU Affero General Public License for more details.
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You should have received a copy of the GNU Affero General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "rnrad1.h"
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using namespace ad9862;
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rnrad1Rx::rnrad1Rx (int whichBoard,
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unsigned int wDecimRate,
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const std::string fpgaFilename = "",
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const std::string firmwareFilename = "")
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: rnrad1Core(whichBoard,RAD1_RX_INTERFACE,RAD1_RX_ALTINTERFACE,fpgaFilename,firmwareFilename,false)
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{
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mDevHandle = 0;
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mEndptHandle = 0;
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mBytesSeen = 0;
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mEnabled = false;
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mDecimRate = wDecimRate;
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// initialize rx specific registers
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// initialize registers that are common to rx and tx
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bool result=true;
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result &= write9862(REG_RX_PWR_DN,0);
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result &= write9862(REG_RX_A,0); // minimum gain = 0x00 (max gain = 0x14)
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result &= write9862(REG_RX_B,0); // minimum gain = 0x00 (max gain = 0x14)
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result &= write9862(REG_RX_MISC,RX_MISC_HS_DUTY_CYCLE | RX_MISC_CLK_DUTY);
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result &= write9862(REG_RX_IF,RX_IF_USE_CLKOUT1 | RX_IF_2S_COMP);
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result &= write9862(REG_RX_DIGITAL,RX_DIGITAL_2_CHAN);
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if (!result) {
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LOG(ERR) << "Failed to init AD9862 RX regs";
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exit(1);
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}
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// Reset the rx path and leave it disabled.
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enable (false);
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sendRqst(VRQ_FPGA_SET_RX_RESET, 1);
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usleep(10);
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sendRqst(VRQ_FPGA_SET_RX_RESET, 0);
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setSampleRateDivisor (2); // usually correct
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setDcOffsetClEnable(0xf, 0xf); // enable DC offset removal control loops
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// check fusb buffering parameters
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int blockSize = 4096; //fusb::default_block_size();
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int numBlocks = 128; //std::max (1, fusb::default_buffer_size() / blockSize);
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mDevHandle = fusb::make_devhandle (getHandle(), getContext());
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mEndptHandle = mDevHandle->make_ephandle (RAD1_RX_ENDPOINT, true,
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blockSize, numBlocks);
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writeFpgaReg(FR_ATR_MASK_1,0);
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writeFpgaReg(FR_ATR_TXVAL_1,0);
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writeFpgaReg(FR_ATR_RXVAL_1,0);
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writeFpgaReg(FR_ATR_MASK_3,0);
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writeFpgaReg(FR_ATR_TXVAL_3,0);
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writeFpgaReg(FR_ATR_RXVAL_3,0);
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mSwMux = 0;
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mHwMux = 0;
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writeFpgaReg(FR_RX_FORMAT,0x00000300);
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writeHwMuxReg();
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setDecimRate(mDecimRate);
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unsigned int mux = 0x00000010;
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setMux(mux);
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writeFpgaReg(FR_MODE, 0);
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setRxFreq(0);
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}
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rnrad1Rx::~rnrad1Rx()
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{
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enable (false);
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delete mEndptHandle;
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delete mDevHandle;
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// initialize registers that are common to rx and tx
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bool result= write9862(REG_RX_PWR_DN,0x1);
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}
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bool rnrad1Rx::writeHwMuxReg()
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{
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bool s = disable();
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bool ok = writeFpgaReg (FR_RX_MUX, mHwMux | 1);
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restore (s);
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return ok;
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}
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bool rnrad1Rx::setRxFreq (double freq)
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{
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int v = (int) rint (freq / (double) adcRate() * pow (2.0, 32.0));
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mRxFreq = v * (double) adcRate() / pow (2.0, 32.0);
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return writeFpgaReg (FR_RX_FREQ_0, v);
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}
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rnrad1Rx *rnrad1Rx::make(int whichBoard,
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unsigned int wDecimRate,
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const std::string fpgaFilename = "",
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const std::string firmwareFilename = "")
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{
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try {
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rnrad1Rx *u = new rnrad1Rx(whichBoard,
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wDecimRate,
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fpgaFilename,
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firmwareFilename);
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return u;
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}
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catch (...) {
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return NULL;
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}
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}
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bool rnrad1Rx::setDecimRate (unsigned int rate)
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{
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if ((rate & 0x1) || rate < 4 || rate > 256){
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LOG(ERR) << "decimation rate must be EVEN and in [4, 256]";
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return false;
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}
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mDecimRate = rate;
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setUsbDataRate ((adcRate()/rate) * (2 * sizeof (short)));
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bool s = disable ();
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int v = mDecimRate/2 - 1;
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bool ok = writeFpgaReg (FR_DECIM_RATE, v);
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restore (s);
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return ok;
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}
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bool rnrad1Rx::setMux (int mux)
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{
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int mHwMux = 0;
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for (int i = 0; i < 8; i++){
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int t = (mux >> (4 * i)) & 0x3;
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mHwMux |= t << (2 * i + 4);
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}
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mSwMux = mux;
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return writeHwMuxReg ();
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}
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bool rnrad1Rx::start()
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{
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if (!rnrad1Core::start ()) // invoke parent's method
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return false;
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// fire off reads before asserting rx_enable
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if (!mEndptHandle->start ()){
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LOG(ERR) << "Can't start USB RX stream";
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return false;
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}
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if (!enable (true)){
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LOG(ERR) << "Can't enable RX";
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return false;
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}
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return true;
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}
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bool rnrad1Rx::setSampleRateDivisor (unsigned int div)
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{
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return writeFpgaReg (FR_RX_SAMPLE_RATE_DIV, div - 1);
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}
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int rnrad1Rx::read (void *buf, int len, bool *overrun)
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{
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int r;
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if (overrun) *overrun = false;
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if (len < 0 || (len % 512) != 0){
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LOG(ERR) << "read: invalid length = " << len;
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return -1;
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}
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r = mEndptHandle->read (buf, len);
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if (r > 0) mBytesSeen += r;
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if (overrun != 0 && mBytesSeen >= mBytesPerPoll){
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mBytesSeen = 0;
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*overrun = true;
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unsigned char status;
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if (checkOverrun(&status) != 1)
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LOG(ERR) << "Overrun check failed";
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*overrun = status;
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}
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return r;
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}
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bool rnrad1Rx::enable (bool on)
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{
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mEnabled = on;
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return (sendRqst(VRQ_FPGA_SET_RX_ENABLE, on) == 0);
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}
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// conditional disable, return prev state
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bool rnrad1Rx::disable ()
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{
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bool enabled = enable ();
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if (enabled) enable (false);
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return enabled;
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}
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// conditional set
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void rnrad1Rx::restore (bool on)
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{
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if (on != enable ()) enable (on);
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}
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bool rnrad1Rx::setPga (int amp, double gain)
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{
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if (amp < 0 || amp > 1)
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return false;
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gain = std::min(pgaMax(), std::max(pgaMin(), gain));
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int intGain = (int) rint((gain - pgaMin()) / pgaDbPerStep());
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int reg = (amp & 1 == 0) ? REG_RX_A : REG_RX_B;
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// read current value to get input buffer bypass flag.
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unsigned char curRx;
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if (!read9862(reg, &curRx))
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return false;
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curRx = (curRx & RX_X_BYPASS_INPUT_BUFFER) | (intGain & 0x7f);
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return write9862(reg, curRx);
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}
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double rnrad1Rx::pga (int amp) const
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{
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if (amp < 0 || amp > 1) return READ_FAILED;
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int reg = (amp & 1 == 0) ? REG_RX_A : REG_RX_B;
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unsigned char v;
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if (!read9862 (reg, &v)) return READ_FAILED;
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return (pgaDbPerStep() * (v & 0x1f)) + pgaMin();
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}
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bool rnrad1Rx::writeOE (int value, int mask)
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{
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return writeFpgaReg(FR_OE_1, (mask << 16) | (value & 0xffff));
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}
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bool rnrad1Rx::writeIO (int value, int mask)
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{
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return writeFpgaReg(FR_IO_1, (mask << 16) | (value & 0xffff));
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}
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bool rnrad1Rx::readIO (int *value)
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{
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int t;
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int reg = 0 + 1; // FIXME, *very* magic number (fix in serial_io.v)
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if (!readFpgaReg(reg, &t)) return false;
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*value = (t >> 16) & 0xffff; // FIXME, more magic
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return true;
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}
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int rnrad1Rx::readIO (void)
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{
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int value;
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if (!readIO(&value)) return READ_FAILED;
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return value;
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}
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bool rnrad1Rx::writeRefClk(int value)
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{
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return writeFpgaReg(FR_RX_A_REFCLK, value);
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}
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bool rnrad1Rx::writeAuxDac (int dac, int value)
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{
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return rnrad1Core::writeAuxDac(dac, value);
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}
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bool rnrad1Rx::readAuxAdc (int adc, int *value)
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{
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return rnrad1Core::readAuxAdc(false, adc, value);
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}
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int rnrad1Rx::readAuxAdc (int adc)
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{
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int retVal;
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rnrad1Rx::readAuxAdc(adc, &retVal);
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return retVal;
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}
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int rnrad1Rx::blockSize() const { return mEndptHandle->block_size(); }
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