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git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@3457 19bc5d8c-e614-43d4-8b26-e1612bc8e597
25 lines
493 B
Verilog
25 lines
493 B
Verilog
module usb_fifo_reader (
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input usbclk,
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input bus_reset,
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input RD,
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output rdreq,
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);
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// FX2 Bug Fix
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reg [8:0] read_count;
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always @(negedge usbclk)
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if(bus_reset)
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read_count <= #1 9'd0;
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else if(RD & ~read_count[8])
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read_count <= #1 read_count + 9'd1;
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else
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read_count <= #1 RD ? read_count : 9'b0;
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assign rdreq = RD & ~read_count[8];
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endmodule
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