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36 lines
1.2 KiB
C
36 lines
1.2 KiB
C
/*
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* Copyright 2014 Range Networks, Inc.
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*
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* This software is distributed under multiple licenses; see the COPYING file in the main directory for licensing information for this specific distribution.
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*
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* This use of this software may be subject to additional restrictions.
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* See the LEGAL file in the main directory for details.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*/
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/*
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* We've now split the RAD1 into 3 separate interfaces.
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*
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* Interface 0 contains only ep0 and is used for command and status.
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* Interface 1 is the Tx path and it uses ep2 OUT BULK.
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* Interface 2 is the Rx path and it uses ep6 IN BULK.
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*/
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#define RAD1_CMD_INTERFACE 0
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#define RAD1_CMD_ALTINTERFACE 0
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#define RAD1_CMD_ENDPOINT 0
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#define RAD1_TX_INTERFACE 1
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#define RAD1_TX_ALTINTERFACE 0
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#define RAD1_TX_ENDPOINT 2 // streaming data from host to FPGA
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#define RAD1_RX_INTERFACE 2
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#define RAD1_RX_ALTINTERFACE 0
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#define RAD1_RX_ENDPOINT 6 // streaming data from FPGA to host
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