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https://github.com/RangeNetworks/openbts.git
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2f40797d0f
git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@3457 19bc5d8c-e614-43d4-8b26-e1612bc8e597
90 lines
2.6 KiB
Verilog
90 lines
2.6 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
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parameter bw = 16;
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parameter N = 4;
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parameter log2_of_max_rate = 7;
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parameter maxbitgain = (N-1)*log2_of_max_rate;
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input clock;
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input reset;
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input enable;
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input [7:0] rate;
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input strobe_in,strobe_out;
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input [bw-1:0] signal_in;
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wire [bw-1:0] signal_in;
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output [bw-1:0] signal_out;
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wire [bw-1:0] signal_out;
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wire [bw+maxbitgain-1:0] signal_in_ext;
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reg [bw+maxbitgain-1:0] integrator [0:N-1];
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reg [bw+maxbitgain-1:0] differentiator [0:N-1];
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reg [bw+maxbitgain-1:0] pipeline [0:N-1];
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integer i;
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sign_extend #(bw,bw+maxbitgain)
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ext_input (.in(signal_in),.out(signal_in_ext));
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//FIXME Note that this section has pipe and diff reversed
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// It still works, but is confusing
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always @(posedge clock)
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if(reset)
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for(i=0;i<N;i=i+1)
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integrator[i] <= #1 0;
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else if (enable & strobe_out)
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begin
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if(strobe_in)
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integrator[0] <= #1 integrator[0] + pipeline[N-1];
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for(i=1;i<N;i=i+1)
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integrator[i] <= #1 integrator[i] + integrator[i-1];
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end
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always @(posedge clock)
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if(reset)
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begin
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for(i=0;i<N;i=i+1)
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begin
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differentiator[i] <= #1 0;
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pipeline[i] <= #1 0;
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end
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end
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else if (enable && strobe_in)
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begin
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differentiator[0] <= #1 signal_in_ext;
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pipeline[0] <= #1 signal_in_ext - differentiator[0];
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for(i=1;i<N;i=i+1)
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begin
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differentiator[i] <= #1 pipeline[i-1];
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pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
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end
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end
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wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
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cic_int_shifter #(bw)
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cic_int_shifter(rate,signal_out_unnorm,signal_out);
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endmodule // cic_interp
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