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2f40797d0f
git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@3457 19bc5d8c-e614-43d4-8b26-e1612bc8e597
48 lines
1.3 KiB
Verilog
48 lines
1.3 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
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parameter depth = 4;
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parameter width = 16;
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parameter size = 16;
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input wclk;
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input [width-1:0] wdata;
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input [depth-1:0] waddr;
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input wen;
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input rclk;
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output reg [width-1:0] rdata;
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input [depth-1:0] raddr;
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reg [width-1:0] ram [0:size-1];
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always @(posedge wclk)
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if(wen)
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ram[waddr] <= #1 wdata;
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always @(posedge rclk)
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rdata <= #1 ram[raddr];
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endmodule // dpram
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