mirror of
https://github.com/RangeNetworks/openbts.git
synced 2025-11-03 21:33:15 +00:00
664 lines
18 KiB
C++
664 lines
18 KiB
C++
/*
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* Copyright 2008, 2009, 2014 Free Software Foundation, Inc.
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*
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* This software is distributed under the terms of the GNU Public License.
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* See the COPYING file in the main directory for details.
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*
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* This use of this software may be subject to additional restrictions.
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* See the LEGAL file in the main directory for details.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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Compilation Flags
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SWLOOPBACK compile for software loopback testing
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*/
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include "Threads.h"
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#include "RAD1Device.h"
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#include <Logger.h>
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using namespace std;
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unsigned char* write_it(unsigned v, unsigned char *s) {
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s[0] = (v>>16) & 0x0ff;
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s[1] = (v>>8) & 0x0ff;
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s[2] = (v) & 0x0ff;
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return s;
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}
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const double RAD1Device::LO_OFFSET = 6.0e6;
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const double RAD1Device::masterClockRate = (double) 52.0e6;
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bool RAD1Device::compute_regs(double freq,
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unsigned *R,
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unsigned *control,
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unsigned *N,
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double *actual_freq)
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{
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if (freq < 1.2e9) {
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DIV2 = 1;
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freq_mult = 2;
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CP1 = 7;
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CP2 = 7;
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}
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else {
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DIV2 = 0;
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freq_mult = 1;
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// This default value matches the RAD1r3.
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CP1 = 7;
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// This default value matches the RAD1r3.
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CP2 = 7;
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}
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double phdet_freq = 13.0e6/(double) R_DIV;
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int desired_n = (int) round(freq*freq_mult/phdet_freq);
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*actual_freq = desired_n * phdet_freq/freq_mult;
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float B = floor(desired_n/16);
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float A = desired_n - 16*B;
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unsigned B_DIV = int(B);
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unsigned A_DIV = int(A);
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//printf("B: %f, A: %f, B_DIV: %u, A_DIV: %u\n",B,A,B_DIV,A_DIV);
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if (B < A) return false;
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*R = (R_RSV<<22) |
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(BSC << 20) |
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(TEST << 19) |
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(LDP << 18) |
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(ABP << 16) |
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(R_DIV << 2);
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*control = (P<<22) |
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(PD<<20) |
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(CP2 << 17) |
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(CP1 << 14) |
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(PL << 12) |
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(MTLD << 11) |
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(CPG << 10) |
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(CP3S << 9) |
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(PDP << 8) |
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(MUXOUT << 5) |
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(CR << 4) |
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(PC << 2);
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*N = (DIVSEL<<23) |
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(DIV2<<22) |
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(CPGAIN<<21) |
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(B_DIV<<8) |
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(N_RSV<<7) |
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(A_DIV<<2);
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return true;
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}
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bool RAD1Device::tx_setFreq(double freq, double *actual_freq)
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{
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unsigned R, control, N;
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if (!compute_regs(freq, &R, &control, &N, actual_freq)) return false;
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if (R==0) return false;
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unsigned char result[3];
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writeLock.lock();
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m_uTx->writeSpi(0,SPI_ENABLE_TX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((R & ~0x3) | 1, result),3);
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m_uTx->writeSpi(0,SPI_ENABLE_TX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((control & ~0x3) | 0, result),3);
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usleep(10000);
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m_uTx->writeSpi(0,SPI_ENABLE_TX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((N & ~0x3) | 2,result),3);
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writeLock.unlock();
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if (m_uTx->readIO() & PLL_LOCK_DETECT) return true;
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if (m_uTx->readIO() & PLL_LOCK_DETECT) return true;
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return false;
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}
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bool RAD1Device::rx_setFreq(double freq, double *actual_freq)
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{
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unsigned R, control, N;
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if (!compute_regs(freq, &R, &control, &N, actual_freq)) return false;
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if (R==0) return false;
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unsigned char result[3];
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writeLock.lock();
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m_uRx->writeSpi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((R & ~0x3) | 1, result), 3);
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m_uRx->writeSpi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((control & ~0x3) | 0, result), 3);
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usleep(10000);
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m_uRx->writeSpi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((N & ~0x3) | 2, result), 3);
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writeLock.unlock();
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usleep(100000);
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if (m_uRx->readIO() & PLL_LOCK_DETECT) return true;
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if (m_uRx->readIO() & PLL_LOCK_DETECT) return true;
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return true; //return false;
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}
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RAD1Device::RAD1Device (double _desiredSampleRate)
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{
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LOG(INFO) << "creating RAD1 device...";
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decimRate = (unsigned int) round(masterClockRate/_desiredSampleRate);
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actualSampleRate = masterClockRate/decimRate;
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rxGain = 0;
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// This default value matches the RAD1r3.
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PC = 0; // bits 3,2 Core power 15mA
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#ifdef SWLOOPBACK
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samplePeriod = 1.0e6/actualSampleRate;
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loopbackBufferSize = 0;
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gettimeofday(&lastReadTime,NULL);
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firstRead = false;
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#endif
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}
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bool RAD1Device::make(bool wSkipRx, int devID)
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{
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skipRx = wSkipRx;
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writeLock.unlock();
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LOG(INFO) << "making RAD1 device..";
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#ifndef SWLOOPBACK
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string rbf = "fpga.rbf";
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if (!skipRx) {
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try {
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m_uRx = rnrad1Rx::make(devID,decimRate, rbf,"ezusb.ihx");
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m_uRx->setFpgaMasterClockFreq(masterClockRate);
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}
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catch(...) {
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LOG(ERR) << "make failed on Rx";
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return false;
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}
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if (m_uRx->fpgaMasterClockFreq() != masterClockRate)
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{
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LOG(ERR) << "WRONG FPGA clock freq = " << m_uRx->fpgaMasterClockFreq()
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<< ", desired clock freq = " << masterClockRate;
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return false;
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}
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m_uRx->writeOE(0,0xffff);
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m_uRx->writeOE((POWER_UP|RX_TXN|ENABLE), 0xffff);
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m_uRx->writeIO((POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
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// FIXME -- This should be configurable.
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setRxGain(47); //maxRxGain());
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}
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try {
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m_uTx = rnrad1Tx::make(devID,decimRate*2, rbf,"ezusb.ihx");
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m_uTx->setFpgaMasterClockFreq(masterClockRate);
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}
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catch(...) {
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LOG(ERR) << "make failed on Tx";
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return false;
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}
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m_uTx->writeOE(0,0xffff);
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m_uTx->writeOE((POWER_UP|RX_TXN|ENABLE), 0xffff);
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m_uTx->writeIO((POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
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if (m_uTx->fpgaMasterClockFreq() != masterClockRate)
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{
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LOG(ERR) << "WRONG FPGA clock freq = " << m_uTx->fpgaMasterClockFreq()
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<< ", desired clock freq = " << masterClockRate;
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return false;
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}
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#endif
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samplesRead = 0;
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samplesWritten = 0;
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started = false;
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return true;
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}
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bool RAD1Device::start()
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{
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LOG(INFO) << "starting RAD1...";
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#ifndef SWLOOPBACK
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if (!m_uRx && !skipRx) return false;
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if (!m_uTx) return false;
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writeLock.lock();
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// power up and configure daughterboards
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m_uTx->writeOE(0,0xffff);
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m_uTx->writeOE((POWER_UP|RX_TXN|ENABLE), 0xffff);
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m_uTx->writeIO((POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
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//m_uTx->writeIO(0,ENABLE,(RX_TXN | ENABLE));
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m_uTx->writeIO((RX_TXN | ENABLE), (RX_TXN | ENABLE));//only for litie
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m_uTx->writeFpgaReg(FR_ATR_MASK_0 ,0);//RX_TXN|ENABLE);
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m_uTx->writeFpgaReg(FR_ATR_TXVAL_0,0);//,0 |ENABLE);
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m_uTx->writeFpgaReg(FR_ATR_RXVAL_0,0);//,RX_TXN|0);
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m_uTx->writeFpgaReg(40,0);
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m_uTx->writeFpgaReg(42,0);
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m_uTx->setPga(0,m_uTx->pgaMax()); // should be 20dB
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m_uTx->setPga(1,m_uTx->pgaMax());
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m_uTx->setMux(0x00000098);
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LOG(INFO) << "TX pgas: " << m_uTx->pga(0) << ", " << m_uTx->pga(1);
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writeLock.unlock();
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if (!skipRx) {
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writeLock.lock();
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m_uRx->writeFpgaReg(FR_ATR_MASK_0 + 1*3,0);
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m_uRx->writeFpgaReg(FR_ATR_TXVAL_0 + 1*3,0);
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m_uRx->writeFpgaReg(FR_ATR_RXVAL_0 + 1*3,0);
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m_uRx->writeFpgaReg(41,0);
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m_uRx->writeOE((POWER_UP|RX_TXN|ENABLE), 0xffff);
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m_uRx->writeIO((POWER_UP|RX_TXN|ENABLE),(POWER_UP|RX_TXN|ENABLE));
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//m_uRx->writeIO(1,0,RX2_RX1N); // using Tx/Rx/
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m_uRx->writeIO(RX2_RX1N,RX2_RX1N); // using Rx2
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m_uRx->setAdcBufferBypass(0,true);
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m_uRx->setAdcBufferBypass(1,true);
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m_uRx->setPga(0,m_uRx->pgaMax()); // should be 20dB
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m_uRx->setPga(1,m_uRx->pgaMax());
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m_uRx->setMux(0x00000010);
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writeLock.unlock();
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}
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data = new short[currDataSize];
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dataStart = 0;
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dataEnd = 0;
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timeStart = 0;
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timeEnd = 0;
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timestampOffset = 0;
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latestWriteTimestamp = 0;
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lastPktTimestamp = 0;
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hi32Timestamp = 0;
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isAligned = false;
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if (!skipRx)
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started = (m_uRx->start() && m_uTx->start());
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else
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started = m_uTx->start();
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return started;
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#else
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gettimeofday(&lastReadTime,NULL);
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return true;
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#endif
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}
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bool RAD1Device::stop()
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{
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#ifndef SWLOOPBACK
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if (!m_uRx) return false;
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if (!m_uTx) return false;
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// power down
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m_uTx->writeIO((~POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
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m_uRx->writeIO(~POWER_UP,(POWER_UP|ENABLE));
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delete[] currData;
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started = false;
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return !started;
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#else
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return true;
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#endif
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}
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double RAD1Device::setTxGain(double dB) {
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writeLock.lock();
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if (dB > maxTxGain()) dB = maxTxGain();
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if (dB < minTxGain()) dB = minTxGain();
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m_uTx->setPga(0,dB);
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m_uTx->setPga(1,dB);
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//LOG(NOTICE) << "Setting TX PGA to " << dB << " dB.";
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writeLock.unlock();
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return dB;
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}
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double RAD1Device::setRxGain(double dB) {
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writeLock.lock();
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if (dB > maxRxGain()) dB = maxRxGain();
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if (dB < minRxGain()) dB = minRxGain();
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double dBret = dB;
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dB = dB - minRxGain();
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double rfMax = 70.0;
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if (dB > rfMax) {
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m_uRx->setPga(0,dB-rfMax);
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m_uRx->setPga(1,dB-rfMax);
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dB = rfMax;
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}
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else {
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m_uRx->setPga(0,0);
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m_uRx->setPga(1,0);
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}
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m_uRx->writeAuxDac(0,
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(int) ceil((1.2 + 0.02 - (dB/rfMax))*4096.0/3.3));
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LOG(DEBUG) << "Setting DAC voltage to " << (1.2+0.02 - (dB/rfMax)) << " " << (int) ceil((1.2 + 0.02 - (dB/rfMax))*4096.0/3.3);
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rxGain = dBret;
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writeLock.unlock();
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return dBret;
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}
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// NOTE: Assumes sequential reads
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int RAD1Device::readSamples(short *buf, int len, bool *overrun,
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TIMESTAMP timestamp,
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bool *underrun,
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unsigned *RSSI)
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{
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#ifndef SWLOOPBACK
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if (!m_uRx) return 0;
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timestamp += timestampOffset;
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if (timestamp + len < timeStart) {
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memset(buf,0,len*2*sizeof(short));
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return len;
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}
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if (underrun) *underrun = false;
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uint32_t readBuf[20000];
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while (1) {
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//guestimate USB read size
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int readLen=0;
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{
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int numSamplesNeeded = timestamp + len - timeEnd;
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if (numSamplesNeeded <=0) break;
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readLen = 512 * ((int) ceil((float) numSamplesNeeded/126.0));
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if (readLen > 8000) readLen= (8000/512)*512;
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}
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// read USRP packets, parse and save A/D data as needed
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readLen = m_uRx->read((void *)readBuf,readLen,overrun);
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for(int pktNum = 0; pktNum < (readLen/512); pktNum++) {
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// tmpBuf points to start of a USB packet
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uint32_t* tmpBuf = (uint32_t *) (readBuf+pktNum*512/4);
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TIMESTAMP pktTimestamp = usrp_to_host_u32(tmpBuf[1]);
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uint32_t word0 = usrp_to_host_u32(tmpBuf[0]);
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uint32_t chan = (word0 >> 16) & 0x1f;
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unsigned payloadSz = word0 & 0x1ff;
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LOG(DEBUG) << "first two bytes: " << hex << word0 << " " << dec << pktTimestamp;
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bool incrementHi32 = ((lastPktTimestamp & 0x0ffffffffll) > pktTimestamp);
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if (incrementHi32 && (timeStart!=0)) {
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LOG(DEBUG) << "high 32 increment!!!";
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hi32Timestamp++;
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}
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pktTimestamp = (((TIMESTAMP) hi32Timestamp) << 32) | pktTimestamp;
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lastPktTimestamp = pktTimestamp;
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if (chan == 0x01f) {
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// control reply, check to see if its ping reply
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uint32_t word2 = usrp_to_host_u32(tmpBuf[2]);
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if ((word2 >> 16) == ((0x01 << 8) | 0x02)) {
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timestamp -= timestampOffset;
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timestampOffset = pktTimestamp - pingTimestamp + PINGOFFSET;
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LOG(DEBUG) << "updating timestamp offset to: " << timestampOffset;
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timestamp += timestampOffset;
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isAligned = true;
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}
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continue;
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}
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if (chan != 0) {
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LOG(DEBUG) << "chan: " << chan << ", timestamp: " << pktTimestamp << ", sz:" << payloadSz;
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continue;
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}
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if ((word0 >> 28) & 0x04) {
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if (underrun) *underrun = true;
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LOG(DEBUG) << "UNDERRUN in TRX->USRP interface";
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}
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if (RSSI) *RSSI = (word0 >> 21) & 0x3f;
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if (!isAligned) continue;
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unsigned cursorStart = pktTimestamp - timeStart + dataStart;
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while (cursorStart*2 > currDataSize) {
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cursorStart -= currDataSize/2;
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}
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if (cursorStart*2 + payloadSz/2 > currDataSize) {
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// need to circle around buffer
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memcpy(data+cursorStart*2,tmpBuf+2,(currDataSize-cursorStart*2)*sizeof(short));
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memcpy(data,tmpBuf+2+(currDataSize/2-cursorStart),payloadSz-(currDataSize-cursorStart*2)*sizeof(short));
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}
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else {
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memcpy(data+cursorStart*2,tmpBuf+2,payloadSz);
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}
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if (pktTimestamp + payloadSz/2/sizeof(short) > timeEnd)
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timeEnd = pktTimestamp+payloadSz/2/sizeof(short);
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//LOG(DEBUG) << "timeStart: " << timeStart << ", timeEnd: " << timeEnd << ", pktTimestamp: " << pktTimestamp;
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}
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}
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// copy desired data to buf
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unsigned bufStart = dataStart+(timestamp-timeStart);
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if (bufStart + len < currDataSize/2) {
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//LOG(DEBUG) << "bufStart: " << bufStart;
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memcpy(buf,data+bufStart*2,len*2*sizeof(short));
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memset(data+bufStart*2,0,len*2*sizeof(short));
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}
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else {
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//LOG(DEBUG) << "len: " << len << ", currDataSize/2: " << currDataSize/2 << ", bufStart: " << bufStart;
|
|
unsigned firstLength = (currDataSize/2-bufStart);
|
|
//LOG(DEBUG) << "firstLength: " << firstLength;
|
|
memcpy(buf,data+bufStart*2,firstLength*2*sizeof(short));
|
|
memset(data+bufStart*2,0,firstLength*2*sizeof(short));
|
|
memcpy(buf+firstLength*2,data,(len-firstLength)*2*sizeof(short));
|
|
memset(data,0,(len-firstLength)*2*sizeof(short));
|
|
}
|
|
dataStart = (bufStart + len) % (currDataSize/2);
|
|
timeStart = timestamp + len;
|
|
|
|
// do IQ swap here
|
|
for (int i = 0; i < len; i++) {
|
|
short tmp = usrp_to_host_short(buf[2*i]);
|
|
buf[2*i] = usrp_to_host_short(buf[2*i+1]);
|
|
buf[2*i+1] = tmp;
|
|
}
|
|
|
|
return len;
|
|
|
|
#else
|
|
if (loopbackBufferSize < 2) return 0;
|
|
int numSamples = 0;
|
|
struct timeval currTime;
|
|
gettimeofday(&currTime,NULL);
|
|
double timeElapsed = (currTime.tv_sec - lastReadTime.tv_sec)*1.0e6 +
|
|
(currTime.tv_usec - lastReadTime.tv_usec);
|
|
if (timeElapsed < samplePeriod) {return 0;}
|
|
int numSamplesToRead = (int) floor(timeElapsed/samplePeriod);
|
|
if (numSamplesToRead < len) return 0;
|
|
|
|
if (numSamplesToRead > len) numSamplesToRead = len;
|
|
if (numSamplesToRead > loopbackBufferSize/2) {
|
|
firstRead =false;
|
|
numSamplesToRead = loopbackBufferSize/2;
|
|
}
|
|
memcpy(buf,loopbackBuffer,sizeof(short)*2*numSamplesToRead);
|
|
loopbackBufferSize -= 2*numSamplesToRead;
|
|
memcpy(loopbackBuffer,loopbackBuffer+2*numSamplesToRead,
|
|
sizeof(short)*loopbackBufferSize);
|
|
numSamples = numSamplesToRead;
|
|
if (firstRead) {
|
|
int new_usec = lastReadTime.tv_usec + (int) round((double) numSamplesToRead * samplePeriod);
|
|
lastReadTime.tv_sec = lastReadTime.tv_sec + new_usec/1000000;
|
|
lastReadTime.tv_usec = new_usec % 1000000;
|
|
}
|
|
else {
|
|
gettimeofday(&lastReadTime,NULL);
|
|
firstRead = true;
|
|
}
|
|
samplesRead += numSamples;
|
|
|
|
return numSamples;
|
|
#endif
|
|
}
|
|
|
|
int RAD1Device::writeSamples(short *buf, int len, bool *underrun,
|
|
unsigned long long timestamp,
|
|
bool isControl)
|
|
{
|
|
writeLock.lock();
|
|
|
|
#ifndef SWLOOPBACK
|
|
if (!m_uTx) return 0;
|
|
|
|
static uint32_t outData[128*200];
|
|
|
|
for (int i = 0; i < len*2; i++) {
|
|
buf[i] = host_to_usrp_short(buf[i]);
|
|
}
|
|
|
|
int numWritten = 0;
|
|
unsigned isStart = 1;
|
|
unsigned RSSI = 0;
|
|
unsigned CHAN = (isControl) ? 0x01f : 0x00;
|
|
len = len*2*sizeof(short);
|
|
int numPkts = (int) ceil((float)len/(float)504);
|
|
unsigned isEnd = (numPkts < 2);
|
|
uint32_t *outPkt = outData;
|
|
int pktNum = 0;
|
|
while (numWritten < len) {
|
|
// pkt is pointer to start of a USB packet
|
|
uint32_t *pkt = outPkt + pktNum*128;
|
|
isEnd = (len - numWritten <= 504);
|
|
unsigned payloadLen = ((len - numWritten) < 504) ? (len-numWritten) : 504;
|
|
pkt[0] = (isStart << 12 | isEnd << 11 | (RSSI & 0x3f) << 5 | CHAN) << 16 | payloadLen;
|
|
pkt[1] = timestamp & 0x0ffffffffll;
|
|
memcpy(pkt+2,buf+(numWritten/sizeof(short)),payloadLen);
|
|
numWritten += payloadLen;
|
|
timestamp += payloadLen/2/sizeof(short);
|
|
isStart = 0;
|
|
pkt[0] = host_to_usrp_u32(pkt[0]);
|
|
pkt[1] = host_to_usrp_u32(pkt[1]);
|
|
pktNum++;
|
|
}
|
|
m_uTx->write((const void*) outPkt,sizeof(uint32_t)*128*numPkts,NULL);
|
|
|
|
samplesWritten += len/2/sizeof(short);
|
|
writeLock.unlock();
|
|
|
|
return len/2/sizeof(short);
|
|
#else
|
|
int retVal = len;
|
|
memcpy(loopbackBuffer+loopbackBufferSize,buf,sizeof(short)*2*len);
|
|
samplesWritten += retVal;
|
|
loopbackBufferSize += retVal*2;
|
|
|
|
return retVal;
|
|
#endif
|
|
}
|
|
|
|
bool RAD1Device::updateAlignment(TIMESTAMP timestamp)
|
|
{
|
|
#ifndef SWLOOPBACK
|
|
short data[] = {0x00,0x02,0x00,0x00};
|
|
uint32_t *wordPtr = (uint32_t *) data;
|
|
bool tmpUnderrun;
|
|
if (writeSamples((short *) data,1,&tmpUnderrun,timestamp & 0x0ffffffffll,true)) {
|
|
pingTimestamp = timestamp;
|
|
return true;
|
|
}
|
|
return false;
|
|
#else
|
|
return true;
|
|
#endif
|
|
}
|
|
|
|
bool RAD1Device::setVCTCXO(unsigned int freq_cal) {
|
|
m_uRx->writeAuxDac(2,freq_cal << 4);
|
|
return true;
|
|
}
|
|
|
|
#ifndef SWLOOPBACK
|
|
bool RAD1Device::setTxFreq(double wFreq, double wAdjFreq) {
|
|
// Tune to wFreq+LO_OFFSET, to prevent LO bleedthrough from interfering with transmitted signal.
|
|
double actFreq;
|
|
unsigned int freq_cal;
|
|
freq_cal = (unsigned int) round(wAdjFreq); //128+round(wAdjFreq/wFreq*5.4e6);
|
|
m_uRx->writeAuxDac(2,freq_cal << 4);
|
|
if (!tx_setFreq(wFreq+1*LO_OFFSET,&actFreq)) return false;
|
|
bool retVal = m_uTx->setTxFreq(wFreq-actFreq);
|
|
LOG(DEBUG) << "set TX: " << wFreq-actFreq << " actual TX: " << m_uTx->txFreq();
|
|
//printf("set TX: %f, set RX: %f\n", wFreq-actFreq, m_uTx->txFreq());
|
|
//only for litie,set pow to maxim,switch on 1W amp
|
|
//m_uRx->writeAuxDac(1,0);
|
|
//m_uRx->writeIO(RX_TXN,RX_TXN);
|
|
|
|
return retVal;
|
|
};
|
|
|
|
bool RAD1Device::setRxFreq(double wFreq, double wAdjFreq) {
|
|
// Tune to wFreq-2*LO_OFFSET, to
|
|
// 1) prevent LO bleedthrough (as with the setTxFreq method above)
|
|
// 2) The extra LO_OFFSET pushes potential transmitter energy (GSM BS->MS transmissions
|
|
// are 45Mhz above MS->BS transmissions) into a notch of the baseband lowpass filter
|
|
// in front of the ADC. This possibly gives us an extra 10-20dB Tx/Rx isolation.
|
|
double actFreq;
|
|
unsigned int freq_cal;
|
|
freq_cal = (unsigned int) round(wAdjFreq); //128+round(wAdjFreq/wFreq*5.4e6);
|
|
m_uRx->writeAuxDac(2,freq_cal << 4);
|
|
if (!rx_setFreq(wFreq-2*LO_OFFSET,&actFreq)) return false;
|
|
bool retVal = m_uRx->setRxFreq(wFreq-actFreq);
|
|
//printf("set RX: %f, actual RX: %f\n",wFreq-actFreq,m_uRx->rxFreq());
|
|
LOG(DEBUG) << "set RX: " << wFreq-actFreq << " actual RX: " << m_uRx->rxFreq();
|
|
|
|
return retVal;
|
|
};
|
|
|
|
#else
|
|
bool RAD1Device::setTxFreq(double wFreq) { return true;};
|
|
bool RAD1Device::setRxFreq(double wFreq) { return true;};
|
|
#endif
|
|
|
|
|