mirror of
https://github.com/RangeNetworks/openbts.git
synced 2025-11-04 05:43:14 +00:00
954 lines
24 KiB
C++
954 lines
24 KiB
C++
/*
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* Copyright 2014 Range Networks, Inc.
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*
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* This software is distributed under multiple licenses; see the COPYING file in the main directory for licensing information for this specific distribution.
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*
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* This use of this software may be subject to additional restrictions.
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* See the LEGAL file in the main directory for details.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*/
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#include "rnrad1Core.h"
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "fpga_regs.h"
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#include <stdexcept>
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#include <assert.h>
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#include <math.h>
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#include "ad9862.h"
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#include <cstdio>
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using namespace ad9862;
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static const double POLLING_INTERVAL = 0.1; // seconds
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static const char *_get_usb_error_str (int usb_err)
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{
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switch (usb_err) {
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case LIBUSB_SUCCESS: return "Success (no error)";
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case LIBUSB_ERROR_IO: return "Input/output error";
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case LIBUSB_ERROR_INVALID_PARAM: return "Invalid parameter";
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case LIBUSB_ERROR_ACCESS: return "Access denied (insufficient permissions)";
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case LIBUSB_ERROR_NO_DEVICE: return "No such device (it may have been disconnected)";
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case LIBUSB_ERROR_NOT_FOUND: return "Entity not found";
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case LIBUSB_ERROR_BUSY: return "Resource busy";
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case LIBUSB_ERROR_TIMEOUT: return "Operation timed out";
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case LIBUSB_ERROR_OVERFLOW: return "Overflow";
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case LIBUSB_ERROR_PIPE: return "Pipe error";
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case LIBUSB_ERROR_INTERRUPTED: return "System call interrupted (perhaps due to signal)";
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case LIBUSB_ERROR_NO_MEM: return "Insufficient memory";
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case LIBUSB_ERROR_NOT_SUPPORTED: return "Operation not supported or unimplemented on this platform";
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case LIBUSB_ERROR_OTHER: return "Unknown error";
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}
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return "Unknown error";
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}
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int usbMsg (struct libusb_device_handle *udh,
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int request, int value, int index,
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unsigned char *bytes, int len)
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{
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int requesttype = (request & 0x80) ? VRT_VENDOR_IN : VRT_VENDOR_OUT;
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int ret = libusb_control_transfer(udh, requesttype, request, value, index,
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bytes, len, 1000);
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if (ret < 0) {
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// we get EPIPE if the firmware stalls the endpoint.
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if (ret != LIBUSB_ERROR_PIPE) {
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LOG(ALERT) << "libusb_control_transfer failed: " << _get_usb_error_str(ret);
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}
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}
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return ret;
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}
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struct libusb_device_handle *rad1OpenInterface (libusb_device *dev, int interface, int altinterface)
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{
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libusb_device_handle *udh;
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int ret;
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if (libusb_open (dev, &udh) < 0) return NULL;
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if (dev != libusb_get_device (udh)){
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LOG(ERR) << "Can't get USB device";
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exit(0);
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}
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if ((ret = libusb_claim_interface (udh, interface)) < 0) {
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LOG(ERR) << "Can't claim USB interface: " << interface << " bc: " << _get_usb_error_str(ret);
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libusb_close (udh);
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return NULL;
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}
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if ((ret = libusb_set_interface_alt_setting (udh, interface,
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altinterface)) < 0) {
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LOG(ERR) << "Can't set USB alt interface: " << altinterface << " bc: " << _get_usb_error_str(ret);
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libusb_release_interface (udh, interface);
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libusb_close (udh);
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return NULL;
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}
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return udh;
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}
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static const int FIRMWARE_HASH_SLOT = 0;
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static const int FPGA_HASH_SLOT = 1;
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static const int hashSlotAddr[2] = {
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RAD1_HASH_SLOT_0_ADDR,
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RAD1_HASH_SLOT_1_ADDR
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};
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bool rad1GetHash (libusb_device_handle *udh, int which,
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unsigned char hash[RAD1_HASH_SIZE])
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{
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which &= 1;
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// we use the Cypress firmware upload command to fetch it.
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int r = libusb_control_transfer (udh, 0xc0, 0xa0, hashSlotAddr[which], 0,
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(unsigned char *) hash, RAD1_HASH_SIZE, 1000);
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if (r < 0) {
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LOG(ERR) << "Failed to get hash, USB err: " << _get_usb_error_str(r);
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}
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return r == RAD1_HASH_SIZE;
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}
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struct libusb_device *rad1FindDevice (int nth, bool allowFx2, libusb_context *ctx)
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{
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libusb_device **list;
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struct libusb_device *q;
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int nFound = 0;
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size_t cnt = libusb_get_device_list(ctx, &list);
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size_t i = 0;
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if (cnt < 0)
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LOG(ERR) << "libusb_get_device_list failed: " <<_get_usb_error_str(cnt);
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for (i = 0; i < cnt; i++) {
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q = list[i];
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libusb_device_descriptor desc;
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int ret = libusb_get_device_descriptor(q, &desc);
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if (ret < 0) {
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LOG(ERR) << "usb_get_device_descriptor failed: " <<_get_usb_error_str(ret);
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}
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if ((desc.idVendor == USB_VID_FSF && desc.idProduct == USB_PID_FSF_RAD1) ||
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(allowFx2 && desc.idVendor == USB_VID_CYPRESS && desc.idProduct == USB_PID_CYPRESS_FX2)) {
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if (nFound == nth) // return this one
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return q;
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nFound++; // keep looking
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}
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}
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// The list needs to be freed. Right now just release it if nothing is found.
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libusb_free_device_list(list, 1);
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return 0; // not found
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}
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static libusb_device_handle *openNthCmdInterface (int nth, libusb_context *ctx)
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{
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libusb_device *udev = rad1FindDevice (nth, false, ctx);
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if (udev == 0){
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LOG(ERR) << "Failed to find rad1 num " << nth;
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return 0;
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}
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libusb_device_handle *udh;
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udh = rad1OpenInterface (udev, RAD1_CMD_INTERFACE, RAD1_CMD_ALTINTERFACE);
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if (udh == 0){
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LOG(ERR) << "Can't open_cmd_interface";
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return 0;
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}
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return udh;
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}
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enum rad1LoadStatus { ULS_ERROR = 0, ULS_OK, ULS_ALREADY_LOADED };
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bool rad1SetHash (libusb_device_handle *udh, int which,
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const unsigned char hash[RAD1_HASH_SIZE])
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{
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which &= 1;
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// we use the Cypress firmware down load command to jam it in.
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int r = libusb_control_transfer (udh, 0x40, 0xa0, hashSlotAddr[which], 0,
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(unsigned char *) hash, RAD1_HASH_SIZE, 1000);
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if (r < 0) {
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LOG(ERR) << "Failed to set hash bc: " << _get_usb_error_str(r);
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}
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return r == RAD1_HASH_SIZE;
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}
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static bool writeRam (libusb_device_handle *udh, unsigned char *buf,
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int startAddr, size_t len)
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{
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int addr;
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int n;
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int a;
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int quanta = MAX_EP0_PKTSIZE;
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for (addr = startAddr; addr < startAddr + (int) len; addr += quanta){
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n = len + startAddr - addr;
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if (n > quanta)
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n = quanta;
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a = libusb_control_transfer(udh, 0x40, 0xA0, addr, 0,
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(unsigned char*)(buf + (addr - startAddr)), n, 1000);
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if (a < 0){
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LOG(ERR) << "Write to RAM failed bc: " << _get_usb_error_str(a);
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return false;
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}
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}
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return true;
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}
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// Load intel format file into cypress FX2 (8051)
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bool rad1LoadFirmware (libusb_device_handle *udh, const char *filename,
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unsigned char hash[RAD1_HASH_SIZE])
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{
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FILE *f = fopen (filename, "ra");
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if (f == 0){
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perror (filename);
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return false;
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}
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// hold CPU in reset while loading firmware
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unsigned char reset = 1;
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if (!writeRam (udh, &reset, 0xE600, 1))
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goto fail;
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char s[1024];
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int length;
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int addr;
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int type;
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unsigned char data[256];
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unsigned char checksum, a;
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unsigned int b;
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int i;
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while (!feof(f)){
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char *shut_up_gcc = fgets(s, sizeof (s), f); /* we should not use more than 263 bytes normally */
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if(s[0]!=':'){
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LOG(ERR) "File " << filename << " has invalid line: " << s;
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goto fail;
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}
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sscanf(s+1, "%02x", &length);
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sscanf(s+3, "%04x", &addr);
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sscanf(s+7, "%02x", &type);
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if(type==0){
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a=length+(addr &0xff)+(addr>>8)+type;
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for(i=0;i<length;i++){
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sscanf (s+9+i*2,"%02x", &b);
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data[i]=b;
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a=a+data[i];
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}
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sscanf (s+9+length*2,"%02x", &b);
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checksum=b;
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if (((a+checksum)&0xff)!=0x00){
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LOG(ERR) << "Checksum failed: got " << (unsigned int) -a << " expected " << (unsigned int) checksum;
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goto fail;
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}
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if (!writeRam (udh, data, addr, length))
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goto fail;
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}
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else if (type == 0x01){ // EOF
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break;
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}
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else if (type == 0x02){
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LOG(ERR) << "Extended address: " << s;
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goto fail;
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}
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}
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// we jam the hash value into the FX2 memory before letting
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// the cpu out of reset. When it comes out of reset it
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// may renumerate which will invalidate udh.
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if (!rad1SetHash (udh, FIRMWARE_HASH_SLOT, hash))
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LOG(ERR) << "Failed to write firmware hash";
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// take CPU out of reset
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reset = 0;
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if (!writeRam (udh, &reset, 0xE600, 1))
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goto fail;
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fclose (f);
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return true;
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fail:
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fclose (f);
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return false;
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}
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// ----------------------------------------------------------------
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// load fpga
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bool rad1LoadFpga (libusb_device_handle *udh, const char *filename,
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unsigned char hash[RAD1_HASH_SIZE])
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{
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bool ok = true;
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FILE *fp = fopen (filename, "rb");
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if (fp == 0){
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perror (filename);
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return false;
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}
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unsigned char buf[MAX_EP0_PKTSIZE]; // 64 is max size of EP0 packet on FX2
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int n;
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usbMsg (udh, VRQ_SET_LED, 1, 1, 0, 0);
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// reset FPGA (and on rev1 both AD9862's, thus killing clock)
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usbMsg(udh, VRQ_FPGA_SET_RESET, 1, 0, 0, 0); // hold fpga in reset
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if (usbMsg (udh, VRQ_FPGA_LOAD, 0, FL_BEGIN, 0, 0) != 0)
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goto fail;
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while ((n = fread (buf, 1, sizeof (buf), fp)) > 0){
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if (usbMsg (udh, VRQ_FPGA_LOAD, 0, FL_XFER, buf, n) != n)
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goto fail;
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}
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if (usbMsg (udh, VRQ_FPGA_LOAD, 0, FL_END, 0, 0) != 0)
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goto fail;
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fclose (fp);
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if (!rad1SetHash (udh, FPGA_HASH_SLOT, hash))
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LOG(ERR) << "Failed to write FPGA hash";
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// On the rev1 RAD1, the {tx,rx}_{enable,reset} bits are
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// controlled over the serial bus, and hence aren't observed until
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// we've got a good fpga bitstream loaded.
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usbMsg(udh, VRQ_FPGA_SET_RESET, 0, 0, 0, 0); // fpga out of master reset
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// now these commands will work
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ok &= (usbMsg(udh, VRQ_FPGA_SET_TX_ENABLE, 0, 0, 0, 0)!=0);
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ok &= (usbMsg(udh, VRQ_FPGA_SET_RX_ENABLE, 0, 0, 0, 0)!=0);
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ok &= (usbMsg(udh, VRQ_FPGA_SET_TX_RESET , 1, 0, 0, 0)!=0);
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ok &= (usbMsg(udh, VRQ_FPGA_SET_RX_RESET , 1, 0, 0, 0)!=0);
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ok &= (usbMsg(udh, VRQ_FPGA_SET_TX_RESET , 0, 0, 0, 0)!=0);
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ok &= (usbMsg(udh, VRQ_FPGA_SET_RX_RESET , 0, 0, 0, 0)!=0);
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if (!ok)
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LOG(NOTICE) << "Failed to reset TX/RX path";
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// Manually reset all regs except master control to zero.
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// FIXME may want to remove this when we rework FPGA reset strategy.
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// In the mean while, this gets us reproducible behavior.
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// FIXME!!!
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for (int i = 0; i < FR_USER_0; i++){
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if (i == FR_MASTER_CTRL)
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continue;
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buf[0] = (0 >> 24) & 0xff; // MSB first
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buf[1] = (0 >> 16) & 0xff;
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buf[2] = (0 >> 8) & 0xff;
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buf[3] = (0 >> 0) & 0xff;
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usbMsg (udh, VRQ_SPI_WRITE,
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0x00 | (i & 0x7f),
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((SPI_ENABLE_FPGA & 0xff) << 8) | ((SPI_FMT_MSB | SPI_FMT_HDR_1) & 0xff),
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buf, 4);
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//rad1writeFpgaReg(udh, i, 0);
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}
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usbMsg (udh, VRQ_SET_LED, 1, 0, 0, 0); // led 1 off
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return true;
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fail:
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fclose (fp);
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return false;
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}
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bool computeHash (const char *filename, unsigned char hash[RAD1_HASH_SIZE])
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{
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assert (RAD1_HASH_SIZE == 16);
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memset (hash, 0, RAD1_HASH_SIZE);
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FILE *fp = fopen (filename, "rb");
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if (fp == 0){
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perror (filename);
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return false;
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}
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int i = 0;
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while (!feof(fp)) {getc(fp);i++;}
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sprintf((char *)hash,"%d",i);
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//int r = md5_stream (fp, (void*) hash);
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fclose (fp);
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return true;
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}
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rad1LoadStatus rad1LoadFirmwareNth (int nth, const char *filename, bool force, libusb_context *ctx)
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{
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libusb_device_handle *udh = openNthCmdInterface (nth, ctx);
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if (udh == 0)
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return ULS_ERROR;
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rad1LoadStatus s;
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unsigned char file_hash[RAD1_HASH_SIZE];
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unsigned char rad1_hash[RAD1_HASH_SIZE];
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if (access (filename, R_OK) != 0){
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perror (filename);
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s = ULS_ERROR;
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}
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else if (!computeHash (filename, file_hash))
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s = ULS_ERROR;
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else if (!force
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&& rad1GetHash (udh, FIRMWARE_HASH_SLOT, rad1_hash)
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&& memcmp (file_hash, rad1_hash, RAD1_HASH_SIZE) == 0) {
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//printf("hash: %s %s\n",file_hash,rad1_hash);
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s = ULS_ALREADY_LOADED;
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}
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else if (!rad1LoadFirmware(udh, filename, file_hash))
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s = ULS_ERROR;
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else
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s = ULS_OK;
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libusb_close(udh);
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switch (s){
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case ULS_ALREADY_LOADED: // nothing changed...
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return ULS_ALREADY_LOADED;
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break;
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case ULS_OK:
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// we loaded firmware successfully.
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// It's highly likely that the board will renumerate (simulate a
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// disconnect/reconnect sequence), invalidating our current
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// handle.
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// FIXME. Turn this into a loop that rescans until we refind ourselves
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sleep(2);
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return ULS_OK;
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default:
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case ULS_ERROR: // some kind of problem
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return ULS_ERROR;
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}
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}
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static void load_status_msg (rad1LoadStatus s, const char *type, const char *filename)
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{
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switch (s){
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case ULS_ERROR:
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LOG(ERR) << "Failed to load " << type << " " << filename;
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break;
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case ULS_ALREADY_LOADED:
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//LOG(ERR) << "Failed to already loaded " << type << " " << filename;
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break;
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case ULS_OK:
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break;
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}
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}
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bool rad1_load_standard_bits (int nth, bool force,
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const std::string fpga_filename,
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const std::string firmware_filename,
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libusb_context *ctx)
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{
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rad1LoadStatus s;
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const char *filename;
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const char *proto_filename;
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int hw_rev;
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// start by loading the firmware
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s = rad1LoadFirmwareNth (nth, firmware_filename.data(), force, ctx);
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load_status_msg (s, "firmware", firmware_filename.data());
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if (s == ULS_ERROR)
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return false;
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// if we actually loaded firmware, we must reload fpga ...
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if (s == ULS_OK)
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force = true;
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libusb_device_handle *udh = openNthCmdInterface (nth, ctx);
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if (udh == 0)
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return false;
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unsigned char file_hash[RAD1_HASH_SIZE];
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unsigned char rad1_hash[RAD1_HASH_SIZE];
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filename = fpga_filename.data();
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if (access (filename, R_OK) != 0){
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perror (filename);
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s = ULS_ERROR;
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}
|
|
else if (!computeHash (filename, file_hash))
|
|
s = ULS_ERROR;
|
|
else if (!force
|
|
&& rad1GetHash (udh, FPGA_HASH_SLOT, rad1_hash)
|
|
&& memcmp (file_hash, rad1_hash, RAD1_HASH_SIZE) == 0) {
|
|
s = ULS_ALREADY_LOADED;
|
|
//printf("hash: %s %s\n",file_hash,rad1_hash);
|
|
}
|
|
else if (!rad1LoadFpga(udh, filename, file_hash))
|
|
s = ULS_ERROR;
|
|
else
|
|
s = ULS_OK;
|
|
|
|
libusb_close(udh);
|
|
load_status_msg (s, "fpga bitstream", fpga_filename.data());
|
|
|
|
if (s == ULS_ERROR)
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
rnrad1Core::rnrad1Core (int which_board,
|
|
int interface, int altInterface,
|
|
const std::string fpga_filename = "",
|
|
const std::string firmware_filename = "",
|
|
bool skipLoad = false)
|
|
{
|
|
mudh = 0;
|
|
mctx = 0;
|
|
mUsbDataRate = 16000000;
|
|
mBytesPerPoll = ((int) POLLING_INTERVAL*mUsbDataRate);
|
|
mFpgaMasterClockFreq = 52000000;
|
|
|
|
memset (mFpgaShadows, 0, sizeof (mFpgaShadows));
|
|
LOG(INFO) << "rad1Core starting on board number "<<which_board+1;
|
|
|
|
if (libusb_init (&mctx) < 0)
|
|
LOG(ERR) << "libusb_init failed";
|
|
|
|
if (!skipLoad) {
|
|
if (!rad1_load_standard_bits (which_board, false, fpga_filename,
|
|
firmware_filename, mctx)) {
|
|
LOG(ERR) << "File load failed";
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
libusb_device *dev = rad1FindDevice (which_board, false, mctx);
|
|
if (dev == 0){
|
|
LOG(ERR) << "Can't find RAD1 board (zero-based number) " << which_board;
|
|
exit(1);
|
|
}
|
|
|
|
libusb_device_descriptor desc;
|
|
int ret = libusb_get_device_descriptor(dev, &desc);
|
|
if (ret < 0) {
|
|
LOG(ERR) << "usb_get_device_descriptor failed: " <<_get_usb_error_str(ret);
|
|
}
|
|
|
|
if ((desc.idVendor == USB_VID_FSF && desc.idProduct == USB_PID_FSF_RAD1) && ((desc.bcdDevice & 0xFF00) == 0)) {
|
|
fprintf (stderr, "found unconfigured RAD1; needs firmware.\n");
|
|
}
|
|
|
|
if (desc.idVendor == USB_VID_CYPRESS && desc.idProduct == USB_PID_CYPRESS_FX2){
|
|
fprintf (stderr, "found unconfigured FX2; needs firmware.\n");
|
|
}
|
|
|
|
mudh = rad1OpenInterface (dev, interface, altInterface);
|
|
if (mudh == 0) {
|
|
LOG(ERR) << "Can't open interfaces";
|
|
exit(1);
|
|
}
|
|
|
|
// initialize registers that are common to rx and tx
|
|
bool result=true;
|
|
result &= write9862(REG_GENERAL,0);
|
|
result &= write9862(REG_DLL,DLL_DISABLE_INTERNAL_XTAL_OSC | DLL_MULT_2X | DLL_FAST);
|
|
result &= write9862(REG_CLKOUT,CLKOUT2_EQ_DLL_OVER_2);
|
|
result &= write9862(REG_AUX_ADC_CLK,AUX_ADC_CLK_CLK_OVER_4);
|
|
if (!result) {
|
|
LOG(ERR) << "Failed to set common MSFE regs";
|
|
exit(1);
|
|
}
|
|
|
|
writeFpgaReg (FR_MODE, 0); // ensure we're in normal mode
|
|
writeFpgaReg (FR_DEBUG_EN, 0); // disable debug outputs
|
|
}
|
|
|
|
|
|
rnrad1Core::~rnrad1Core ()
|
|
{
|
|
if (mudh) libusb_close(mudh);
|
|
if (mctx) libusb_exit(mctx);
|
|
}
|
|
|
|
void rnrad1Core::setUsbDataRate (int usb_data_rate) {
|
|
mUsbDataRate = usb_data_rate;
|
|
mBytesPerPoll = (int) (usb_data_rate*POLLING_INTERVAL);
|
|
}
|
|
|
|
int rnrad1Core::sendRqst (int request, bool flag)
|
|
{
|
|
return usbMsg (mudh, request, flag, 0, 0, 0);
|
|
}
|
|
|
|
int rnrad1Core::checkUnderrun(unsigned char *status)
|
|
{
|
|
return usbMsg (mudh, VRQ_GET_STATUS, 0, GS_TX_UNDERRUN,
|
|
status, 1);
|
|
}
|
|
|
|
int rnrad1Core::checkOverrun(unsigned char *status)
|
|
{
|
|
return usbMsg (mudh, VRQ_GET_STATUS, 0, GS_RX_OVERRUN,
|
|
status, 1);
|
|
}
|
|
|
|
bool rnrad1Core::writeI2c (int i2c_addr, unsigned char *buf, int len)
|
|
{
|
|
if (len < 1 || len > MAX_EP0_PKTSIZE)
|
|
return false;
|
|
|
|
return usbMsg (mudh, VRQ_I2C_WRITE, i2c_addr, 0,
|
|
buf, len) == len;
|
|
}
|
|
|
|
bool rnrad1Core::readI2c (int i2c_addr, unsigned char *buf, int len)
|
|
{
|
|
if (len <= 0)
|
|
return false;
|
|
|
|
if (usbMsg (mudh, VRQ_I2C_READ, i2c_addr, 0,
|
|
(unsigned char *) buf, len) != len)
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
bool rnrad1Core::setAdcOffset (int which_adc, int offset)
|
|
{
|
|
if (which_adc < 0 || which_adc > 3)
|
|
return false;
|
|
|
|
return writeFpgaReg (FR_ADC_OFFSET_0 + which_adc, offset);
|
|
}
|
|
|
|
bool rnrad1Core::setDacOffset (int which_dac, int offset, int offset_pin)
|
|
{
|
|
int tx_a = (which_dac & 0x1) == 0;
|
|
int lo = ((offset & 0x3) << 6) | (offset_pin & 0x1);
|
|
int hi = (offset >> 2);
|
|
bool ok;
|
|
|
|
if (tx_a){
|
|
ok = write9862 (REG_TX_A_OFFSET_LO, lo);
|
|
ok &= write9862 (REG_TX_A_OFFSET_HI, hi);
|
|
}
|
|
else {
|
|
ok = write9862 (REG_TX_B_OFFSET_LO, lo);
|
|
ok &= write9862 (REG_TX_B_OFFSET_HI, hi);
|
|
}
|
|
|
|
return ok;
|
|
}
|
|
|
|
bool rnrad1Core::setAdcBufferBypass (int which_adc, bool bypass)
|
|
{
|
|
if (which_adc < 0 || which_adc > 1)
|
|
return false;
|
|
|
|
bool useA = (which_adc & 1) == 0;
|
|
int reg = useA ? REG_RX_A : REG_RX_B;
|
|
|
|
unsigned char cur_rx;
|
|
unsigned char cur_pwr_dn;
|
|
|
|
// If the input buffer is bypassed, we need to power it down too.
|
|
|
|
bool ok = read9862 (reg, &cur_rx);
|
|
ok &= read9862 (REG_RX_PWR_DN, &cur_pwr_dn);
|
|
if (!ok)
|
|
return false;
|
|
|
|
if (bypass){
|
|
cur_rx |= RX_X_BYPASS_INPUT_BUFFER;
|
|
cur_pwr_dn |= (useA ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B);
|
|
}
|
|
else {
|
|
cur_rx &= ~RX_X_BYPASS_INPUT_BUFFER;
|
|
cur_pwr_dn &= ~(useA ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B);
|
|
}
|
|
|
|
ok &= write9862 (reg, cur_rx);
|
|
ok &= write9862 (REG_RX_PWR_DN, cur_pwr_dn);
|
|
return ok;
|
|
}
|
|
|
|
bool rnrad1Core::setDcOffsetClEnable(int bits, int mask)
|
|
{
|
|
return writeFpgaReg(FR_DC_OFFSET_CL_EN,
|
|
(mFpgaShadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits & mask));
|
|
}
|
|
|
|
bool rnrad1Core::writeAuxDac (int which_dac, int value)
|
|
{
|
|
if (!(0 <= which_dac && which_dac < 4)){
|
|
LOG(ERR) << "Write to invalid dac" << which_dac;
|
|
return false;
|
|
}
|
|
|
|
value &= 0x0fff; // mask to 12-bits
|
|
|
|
// dac 0, 1, and 2 are really 8 bits.
|
|
value = value >> 4; // shift value appropriately
|
|
int regno = 36 + which_dac;
|
|
|
|
return write9862(regno, value);
|
|
}
|
|
|
|
bool rnrad1Core::readAuxAdc (bool isTx, int which_adc, int *value)
|
|
{
|
|
*value = 0;
|
|
|
|
unsigned char aux_adc_control =
|
|
AUX_ADC_CTRL_REFSEL_A // on chip reference
|
|
| AUX_ADC_CTRL_REFSEL_B; // on chip reference
|
|
|
|
int rd_reg = 26; // base address of two regs to read for result
|
|
|
|
// program the ADC mux bits
|
|
if (isTx)
|
|
aux_adc_control |= AUX_ADC_CTRL_SELECT_A2 | AUX_ADC_CTRL_SELECT_B2;
|
|
else {
|
|
rd_reg += 2;
|
|
aux_adc_control |= AUX_ADC_CTRL_SELECT_A1 | AUX_ADC_CTRL_SELECT_B1;
|
|
}
|
|
|
|
// I'm not sure if we can set the mux and issue a start conversion
|
|
// in the same cycle, so let's do them one at a time.
|
|
write9862(34, aux_adc_control);
|
|
|
|
if (which_adc == 0)
|
|
aux_adc_control |= AUX_ADC_CTRL_START_A;
|
|
else {
|
|
rd_reg += 4;
|
|
aux_adc_control |= AUX_ADC_CTRL_START_B;
|
|
}
|
|
|
|
// start the conversion
|
|
write9862(34, aux_adc_control);
|
|
|
|
// read the 10-bit result back
|
|
unsigned char v_lo = 0;
|
|
unsigned char v_hi = 0;
|
|
bool r = read9862(rd_reg, &v_lo);
|
|
r &= read9862(rd_reg, &v_hi);
|
|
|
|
if (r)
|
|
*value = ((v_hi << 2) | ((v_lo >> 6) & 0x3)) << 2; // format as 12-bit
|
|
|
|
return r;
|
|
}
|
|
|
|
int rnrad1Core::readAuxAdc (bool isTx, int which_adc)
|
|
{
|
|
int value;
|
|
if (!readAuxAdc (isTx, which_adc, &value))
|
|
return READ_FAILED;
|
|
|
|
return value;
|
|
}
|
|
|
|
|
|
bool rnrad1Core::writeEeprom (int i2c_addr, int eeprom_offset, const std::string buf)
|
|
{
|
|
unsigned char cmd[2];
|
|
const unsigned char *p = (unsigned char *) buf.data();
|
|
|
|
// The simplest thing that could possibly work:
|
|
// all writes are single byte writes.
|
|
//
|
|
// We could speed this up using the page write feature,
|
|
// but we write so infrequently, why bother...
|
|
|
|
int len = buf.size();
|
|
while (len-- > 0){
|
|
cmd[0] = eeprom_offset++;
|
|
cmd[1] = *p++;
|
|
bool r = writeI2c (i2c_addr, cmd, 2);
|
|
usleep (10*1000); // delay 10ms worst case write time
|
|
if (!r)
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
std::string rnrad1Core::readEeprom (int i2c_addr, int eeprom_offset, int len)
|
|
{
|
|
if (len <= 0)
|
|
return "";
|
|
|
|
char buf[len];
|
|
|
|
unsigned char *p = (unsigned char *) buf;
|
|
|
|
// We setup a random read by first doing a "zero byte write".
|
|
// Writes carry an address. Reads use an implicit address.
|
|
|
|
unsigned char cmd[1];
|
|
cmd[0] = eeprom_offset;
|
|
if (!writeI2c(i2c_addr, cmd, 1)) return "";
|
|
|
|
int orig_len = len;
|
|
while (len > 0){
|
|
int n = std::min (len, MAX_EP0_PKTSIZE);
|
|
if (!readI2c(i2c_addr, p, n)) {return "";}
|
|
len -= n;
|
|
p += n;
|
|
}
|
|
|
|
return std::string (buf, orig_len);
|
|
}
|
|
|
|
bool rnrad1Core::setLed (int which_led, bool on)
|
|
{
|
|
int r = usbMsg (mudh, VRQ_SET_LED, on, which_led, 0, 0);
|
|
|
|
return r == 0;
|
|
}
|
|
|
|
bool rnrad1Core::writeFpgaReg (int regno, int value) //< 7-bit regno, 32-bit value
|
|
{
|
|
|
|
if (regno >= 0 && regno < MAX_REGS)
|
|
mFpgaShadows[regno] = value;
|
|
|
|
unsigned char buf[4];
|
|
|
|
buf[0] = (value >> 24) & 0xff; // MSB first
|
|
buf[1] = (value >> 16) & 0xff;
|
|
buf[2] = (value >> 8) & 0xff;
|
|
buf[3] = (value >> 0) & 0xff;
|
|
|
|
return writeSpi (0x00 | (regno & 0x7f),
|
|
SPI_ENABLE_FPGA,
|
|
SPI_FMT_MSB | SPI_FMT_HDR_1,
|
|
buf, 4);
|
|
|
|
}
|
|
|
|
bool rnrad1Core::readFpgaReg (int regno, int *value) //< 7-bit regno, 32-bit value
|
|
{
|
|
*value = 0;
|
|
unsigned char buf[4];
|
|
|
|
bool ok = readSpi (0x80 | (regno & 0x7f),
|
|
SPI_ENABLE_FPGA,
|
|
SPI_FMT_MSB | SPI_FMT_HDR_1,
|
|
buf, 4);
|
|
|
|
if (ok)
|
|
*value = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
|
|
|
|
return ok;
|
|
}
|
|
|
|
|
|
int rnrad1Core::readFpgaReg (int regno)
|
|
{
|
|
int value;
|
|
if (!readFpgaReg (regno, &value))
|
|
return READ_FAILED;
|
|
return value;
|
|
}
|
|
|
|
bool rnrad1Core::write9862 (int regno, unsigned char value)
|
|
{
|
|
unsigned char buf[1];
|
|
|
|
buf[0] = value;
|
|
|
|
return writeSpi(0x00 | (regno & 0x3f),
|
|
SPI_ENABLE_CODEC_A,
|
|
SPI_FMT_MSB | SPI_FMT_HDR_1,
|
|
(unsigned char *) buf, 1);
|
|
}
|
|
|
|
bool rnrad1Core::read9862 (int regno, unsigned char *value) const
|
|
{
|
|
|
|
return readSpi(0x80 | (regno & 0x3f),
|
|
SPI_ENABLE_CODEC_A,
|
|
SPI_FMT_MSB | SPI_FMT_HDR_1,
|
|
value, 1);
|
|
}
|
|
|
|
|
|
int rnrad1Core::read9862 (int regno) const
|
|
{
|
|
unsigned char value;
|
|
if (!read9862 (regno, &value))
|
|
return READ_FAILED;
|
|
return value;
|
|
}
|
|
|
|
|
|
bool rnrad1Core::writeSpi (int optional_header, int enables, int format, unsigned char *buf, int len)
|
|
{
|
|
return (usbMsg (mudh, VRQ_SPI_WRITE,
|
|
optional_header,
|
|
((enables & 0xff) << 8) | (format & 0xff),
|
|
buf, len) == len);
|
|
}
|
|
|
|
|
|
bool rnrad1Core::readSpi (int optional_header, int enables, int format, unsigned char *buf, int len) const
|
|
{
|
|
if (len <= 0 || len > MAX_EP0_PKTSIZE)
|
|
return false;
|
|
|
|
if (usbMsg (mudh, VRQ_SPI_READ,
|
|
optional_header,
|
|
((enables & 0xff) << 8) | (format & 0xff),
|
|
(unsigned char *) buf, len) != len)
|
|
{ return false;}
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
bool rnrad1Core::start()
|
|
{
|
|
return true;
|
|
}
|
|
|