mirror of
https://github.com/RangeNetworks/openbts.git
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2f40797d0f
git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@3457 19bc5d8c-e614-43d4-8b26-e1612bc8e597
108 lines
3.2 KiB
Verilog
108 lines
3.2 KiB
Verilog
module channel_ram
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( // System
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input txclk, input reset,
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// USB side
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input [31:0] datain, input WR, input WR_done, output have_space,
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// Reader side
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output [31:0] dataout, input RD, input RD_done, output packet_waiting);
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reg [6:0] wr_addr, rd_addr;
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reg [1:0] which_ram_wr, which_ram_rd;
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reg [2:0] nb_packets;
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reg [31:0] ram0 [0:127];
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reg [31:0] ram1 [0:127];
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reg [31:0] ram2 [0:127];
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reg [31:0] ram3 [0:127];
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reg [31:0] dataout0;
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reg [31:0] dataout1;
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reg [31:0] dataout2;
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reg [31:0] dataout3;
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wire wr_done_int;
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wire rd_done_int;
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wire [6:0] rd_addr_final;
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wire [1:0] which_ram_rd_final;
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// USB side
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always @(posedge txclk)
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if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
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always @(posedge txclk)
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if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
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always @(posedge txclk)
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if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
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always @(posedge txclk)
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if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
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assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
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always @(posedge txclk)
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if(reset)
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wr_addr <= 0;
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else if (WR_done)
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wr_addr <= 0;
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else if (WR)
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wr_addr <= wr_addr + 7'd1;
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always @(posedge txclk)
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if(reset)
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which_ram_wr <= 0;
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else if (wr_done_int)
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which_ram_wr <= which_ram_wr + 2'd1;
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assign have_space = (nb_packets < 3'd3);
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// Reader side
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// short hand fifo
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// rd_addr_final is what rd_addr is going to be next clock cycle
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// which_ram_rd_final is what which_ram_rd is going to be next clock cycle
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always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
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always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
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always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
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always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
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assign dataout = (which_ram_rd_final[1]) ?
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(which_ram_rd_final[0] ? dataout3 : dataout2) :
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(which_ram_rd_final[0] ? dataout1 : dataout0);
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//RD_done is the only way to signal the end of one packet
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assign rd_done_int = RD_done;
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always @(posedge txclk)
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if (reset)
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rd_addr <= 0;
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else if (RD_done)
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rd_addr <= 0;
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else if (RD)
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rd_addr <= rd_addr + 7'd1;
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assign rd_addr_final = (reset|RD_done) ? (6'd0) :
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((RD)?(rd_addr+7'd1):rd_addr);
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always @(posedge txclk)
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if (reset)
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which_ram_rd <= 0;
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else if (rd_done_int)
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which_ram_rd <= which_ram_rd + 2'd1;
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assign which_ram_rd_final = (reset) ? (2'd0):
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((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
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//packet_waiting is set to zero if rd_done_int is high
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//because there is no guarantee that nb_packets will be pos.
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assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
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always @(posedge txclk)
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if (reset)
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nb_packets <= 0;
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else if (wr_done_int & ~rd_done_int)
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nb_packets <= nb_packets + 3'd1;
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else if (rd_done_int & ~wr_done_int)
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nb_packets <= nb_packets - 3'd1;
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endmodule
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