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https://github.com/RangeNetworks/openbts.git
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5289a229d9
git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@6168 19bc5d8c-e614-43d4-8b26-e1612bc8e597
61 lines
2.5 KiB
C
61 lines
2.5 KiB
C
/*
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* defines for the VRQ_SPI_READ and VRQ_SPI_WRITE commands
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*
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* SPI == "Serial Port Interface". SPI is a 3 wire bus plus a
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* separate enable for each peripheral. The common lines are SCLK,
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* SDI and SDO. The FX2 always drives SCLK and SDI, the clock and
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* data lines from the FX2 to the peripheral. When enabled, a
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* peripheral may drive SDO, the data line from the peripheral to the
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* FX2.
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*
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* The SPI_READ and SPI_WRITE commands are formatted identically.
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* Each specifies which peripherals to enable, whether the bits should
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* be transmistted Most Significant Bit first or Least Significant Bit
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* first, the number of bytes in the optional header, and the number
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* of bytes to read or write in the body.
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*
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* The body is limited to 64 bytes. The optional header may contain
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* 0, 1 or 2 bytes. For an SPI_WRITE, the header bytes are
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* transmitted to the peripheral followed by the the body bytes. For
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* an SPI_READ, the header bytes are transmitted to the peripheral,
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* then len bytes are read back from the peripheral.
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*/
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/*
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* SPI_FMT_* goes in wIndexL
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*/
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#define SPI_FMT_xSB_MASK (1 << 7)
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# define SPI_FMT_LSB (1 << 7) // least signficant bit first
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# define SPI_FMT_MSB (0 << 7) // most significant bit first
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#define SPI_FMT_HDR_MASK (3 << 5)
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# define SPI_FMT_HDR_0 (0 << 5) // 0 header bytes
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# define SPI_FMT_HDR_1 (1 << 5) // 1 header byte
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# define SPI_FMT_HDR_2 (2 << 5) // 2 header bytes
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/*
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* SPI_ENABLE_* goes in wIndexH
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*
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* For the software interface, the enables are active high.
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* For reads, it's an error to have more than one enable set.
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*
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* [FWIW, the hardware implements them as active low. Don't change the
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* definitions of these. They are related to usrp_rev1_regs.h]
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*/
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#define SPI_ENABLE_FPGA 0x01 // select FPGA
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#define SPI_ENABLE_CODEC_A 0x02 // select AD9862 A
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#define SPI_ENABLE_CODEC_B 0x04 // select AD9862 B
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#define SPI_ENABLE_reserved 0x08
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#define SPI_ENABLE_TX_A 0x10 // select d'board TX A
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#define SPI_ENABLE_RX_A 0x20 // select d'board RX A
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#define SPI_ENABLE_TX_B 0x40 // select d'board TX B
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#define SPI_ENABLE_RX_B 0x80 // select d'board RX B
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/*
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* If there's one header byte, it goes in wValueL.
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*
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* If there are two header bytes, they go in wValueH | wValueL.
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* The transmit order of the bytes (and bits within them) is
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* determined by SPI_FMT_*SB
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*/
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