trx: Fix tx/rx-sps 4 for USRP1 devices

The existing code sets the pingOffset variable to -7231(269 - 7500)
with tx-sps = 4. The (apparent) correct value for pingOffset for
tx/rx-sps 4 is 272.

While I'm not completely sure how this patch works to fix the increased
sps value, my theory is that the original OpenBTS TRX  only supported
a split sps setup(tx-sps=4, rx_sps=1 for sps=4), which created
differing decimation rates between Tx and Rx on the board.
In this case, apparently you needed to account for an advance in the
timestamp for a correct output.

With tx_sps == rx_sps, the decimation/sample rates will be the same,
and(I guess) this advance doesn't need to be accounted for.

Also changed a line in the initialization of the Rx end of the USRP
device to use the correct decimation rate when tx/rx-sps == 4.

Since osmo-trx won't allow nonequal values for tx-sps and rx-sps, I
commented out the logic that selected pingOffset based on sps.
I left it visible in the file for reference however.

Tested & working on the URAN-1, a USRP1 clone designed for GSM.

Change-Id: I3b08c23a3e7d4a226cd23b9fe42558f596a63257

Transceiver52M/device/usrp1/USRPDevice.cpp

@@ -75,18 +75,19 @@ USRPDevice::USRPDevice(InterfaceType iface, const struct trx_cfg *cfg) : RadioDe
    * split sample rate Tx/Rx - 4/1 sps we need to need to
    * compensate for advance rather than delay.
    */
-  if (tx_sps == 1)
-    pingOffset = 272;
-  else if (tx_sps == 4)
-    pingOffset = 269 - 7500;
-  else
-    pingOffset = 0;
+  pingOffset = 272;
+
+  /* Split SPS (4/1) unsupported on USRP1
+   * if(tx_sps == 4 && rx_sps == 1)
+   *   pingOffset = 269 - 7500;
+   */
 
 #ifdef SWLOOPBACK
   samplePeriod = 1.0e6/actualSampleRate;
   loopbackBufferSize = 0;
   gettimeofday(&lastReadTime,NULL);
   firstRead = false;
+  pingOffset = 0;
 #endif
 }
 
@@ -101,7 +102,7 @@ int USRPDevice::open()
   m_uRx.reset();
   try {
     m_uRx = usrp_standard_rx_sptr(usrp_standard_rx::make(
-                                        0, decimRate * tx_sps, 1, -1,
+                                        0, decimRate, 1, -1,
                                         usrp_standard_rx::FPGA_MODE_NORMAL,
                                         1024, 16 * 8, rbf));
     m_uRx->set_fpga_master_clock_freq(masterClockRate);