Readme file for UmTRX project is added

README

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+Overview
+========
+
+This branch includes changes to UHD to make it working with Fairwaves UmTRX hardware.
+
+Among other changes it includes ICAP and other assorted FPGA timing issues:
+
+26-JAN-2012: 
+* Fix ICAP timing problems for UmTRX: the maximum clock rate for the ICAP module on the Spartan-6 FPGA is 20 MHz 
+* Add a clk_icap to top level UmTRX design (13 MHz, 180 deg. phase clock generated by pll_clk.xco, a COREGEN module).
+* Add pipeline registers pps signal in ./fpga/usrp2/timing/time_64bit.v
+* Create ./fpga/usrp2/s6_icap_wb.v to clock Spartan-6 ICAP IP Core with clk_icap
+* Modify ./fpga/usrp2/top/N2x0/u2plus_umtrx.v and u2plus_core.v to connect clk_icap (not connected for non-UmTRX designs)
+* Change ISE tool settings based on smartXplorer parameters that meet timing and modify Makefile.UmTRX accordingly.
+
+Notes
+=====
+
+If MAP fails when remaking the UmTRX FPGA bitstream under Ubuntu Linux for ISE v13.3 and below, define:
+
+    LD_PRELOAD="$XILINX/lib/lin/libboost_serialization-gcc41-mt-p-1_38.so.1.38.0"
+
+after sourcing the Xilinx settings and before issuing:
+
+    make -f Makefile.UmTRX