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1 Commits
1.0.15 ... fpga_wip

Author SHA1 Message Date
Sergey Kostanbaev
27d0433be7 fpga: WIP refactoring 2017-08-04 16:01:59 +03:00
11 changed files with 1123 additions and 57 deletions
Expand all files Collapse all files

50
fpga/control_lib/s6_icap_wb.v
View File

@@ -21,50 +21,52 @@
module s6_icap_wb module s6_icap_wb
(input clk, input clk_icap, input reset, (input clk, input clk_icap, input reset,
input cyc_i, input stb_i, input we_i, output reg ack_o, input cyc_i, input stb_i, input we_i, output reg ack_o,
input [31:0] dat_i, output reg[31:0] dat_o);//, output [31:0] debug_out); input [31:0] dat_i, output [31:0] dat_o);//, output [31:0] debug_out);
reg slow_clk_icap; // reg slow_clk_icap;
always @(posedge clk_icap) slow_clk_icap <= ~slow_clk_icap; // always @(posedge clk_icap) slow_clk_icap <= ~slow_clk_icap;
wire BUSY, CE, WRITE; wire BUSY, CE, WRITE;
wire[31:0] s1_dat_i; wire[15:0] s1_dat_i;
reg[31:0] s_dat_o; // reg[31:0] s_dat_o;
wire[31:0] s1_dat_o; // wire[31:0] s1_dat_o;
assign s1_dat_o[31:16] = 16'd0; // assign s1_dat_o[31:16] = 16'd0;
assign dat_o = 0;
wire full, empty; wire full, empty;
fifo_xlnx_16x40_2clk icap_fifo fifo_xlnx_32x36_2clk icap_fifo
(.rst(reset), (.rst(reset),
.wr_clk(clk), .din(dat_i), .wr_en(we_i & stb_i & ~ack_o & ~full), .full(full), .wr_clk(clk), .din(dat_i[15:0]), .wr_en(we_i & cyc_i & stb_i & ~ack_o & ~full), .full(full),
.rd_clk(slow_clk_icap), .dout(s1_dat_i), .rd_en(~empty), .empty(empty)); .rd_clk(clk_icap), .dout(s1_dat_i), .rd_en(~empty), .empty(empty));
assign WRITE = empty; // assign WRITE = empty;
assign CE = empty; assign CE = empty;
ICAP_SPARTAN6 ICAP_SPARTAN6_inst ICAP_SPARTAN6 ICAP_SPARTAN6_inst
(.BUSY(BUSY), // Busy output (.BUSY(), // Busy output, active high
.O(s1_dat_o[15:0]), // 16-bit data output .O(), // 16-bit data output
.CE(CE), // Clock enable input .CE(CE), // Clock enable input, active low
.CLK(slow_clk_icap), // Clock input .CLK(clk_icap), // Clock input
.I(s1_dat_i[15:0]), // 16-bit data input .I(s1_dat_i), // 16-bit data input
.WRITE(WRITE) // Write input .WRITE(1'b0) // Write input, 0 - WRITE, 1 - READ
); );
//cross back to Wishbone clock domain //cross back to Wishbone clock domain
always @(posedge clk) always @(posedge clk)
if (reset) if (reset)
begin begin
s_dat_o <= 32'd0; //s_dat_o <= 32'd0;
dat_o <= 32'd0; //dat_o <= 32'd0;
ack_o <= 1'b0; ack_o <= 1'b0;
end end
else else
begin begin
s_dat_o <= s1_dat_o; // s_dat_o <= s1_dat_o;
dat_o[15:0] <= s_dat_o[15:0]; // dat_o[15:0] <= s_dat_o[15:0];
ack_o <= stb_i & ~ack_o; ack_o <= cyc_i & stb_i & ~ack_o;
end end
endmodule // s6_icap_wb endmodule // s6_icap_wb

10
fpga/coregen/pll_rx.v
View File

@@ -58,6 +58,7 @@
// CLK_OUT1 125.000 0.000 50.0 200.000 50.000 // CLK_OUT1 125.000 0.000 50.0 200.000 50.000
// CLK_OUT2 125.000 180.000 50.0 300.000 50.000 // CLK_OUT2 125.000 180.000 50.0 300.000 50.000
// CLK_OUT3 125.000 0.000 50.0 200.000 50.000 // CLK_OUT3 125.000 0.000 50.0 200.000 50.000
// CLK_OUT4 62.500 0.000 50.0 200.000 50.000
// //
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// Input Clock Input Freq (MHz) Input Jitter (UI) // Input Clock Input Freq (MHz) Input Jitter (UI)
@@ -73,7 +74,8 @@ module pll_rx
// Clock out ports // Clock out ports
output clk_rx, output clk_rx,
output clk_rx_180, output clk_rx_180,
output clk_to_mac output clk_to_mac,
output clk_rx_div2
); );
// Input buffering // Input buffering
@@ -95,6 +97,7 @@ module pll_rx
wire clkfb; wire clkfb;
wire clk0; wire clk0;
wire clk180; wire clk180;
wire clkdv;
DCM_SP DCM_SP
#(.CLKDV_DIVIDE (2.000), #(.CLKDV_DIVIDE (2.000),
@@ -120,7 +123,7 @@ module pll_rx
.CLK2X180 (), .CLK2X180 (),
.CLKFX (), .CLKFX (),
.CLKFX180 (), .CLKFX180 (),
.CLKDV (), .CLKDV (clkdv),
// Ports for dynamic phase shift // Ports for dynamic phase shift
.PSCLK (1'b0), .PSCLK (1'b0),
.PSEN (1'b0), .PSEN (1'b0),
@@ -151,6 +154,9 @@ module pll_rx
(.O (clk_to_mac), (.O (clk_to_mac),
.I (clk0)); .I (clk0));
BUFG clkout4_buf
(.O (clk_rx_div2),
.I (clkdv));
endmodule endmodule

27
fpga/coregen/pll_rx.xco
View File

@@ -1,7 +1,7 @@
############################################################## ##############################################################
# #
# Xilinx Core Generator version 13.1 # Xilinx Core Generator version 14.7
# Date: Sat Jan 07 20:42:05 2012 # Date: Wed Aug 2 17:45:53 2017
# #
############################################################## ##############################################################
# #
@@ -12,12 +12,16 @@
# #
############################################################## ##############################################################
# #
# Generated from component: xilinx.com:ip:Clocking_Wizard:3.6
#
##############################################################
#
# BEGIN Project Options # BEGIN Project Options
SET addpads = false SET addpads = false
SET asysymbol = true SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false SET createndf = false
SET designentry = Advanced SET designentry = Verilog
SET device = xc6slx75 SET device = xc6slx75
SET devicefamily = spartan6 SET devicefamily = spartan6
SET flowvendor = Other SET flowvendor = Other
@@ -27,12 +31,12 @@ SET implementationfiletype = Ngc
SET package = fgg484 SET package = fgg484
SET removerpms = false SET removerpms = false
SET simulationfiles = Behavioral SET simulationfiles = Behavioral
SET speedgrade = -3 SET speedgrade = -2
SET verilogsim = true SET verilogsim = true
SET vhdlsim = true SET vhdlsim = false
# END Project Options # END Project Options
# BEGIN Select # BEGIN Select
SELECT Clocking_Wizard family Xilinx,_Inc. 3.1 SELECT Clocking_Wizard xilinx.com:ip:Clocking_Wizard:3.6
# END Select # END Select
# BEGIN Parameters # BEGIN Parameters
CSET calc_done=DONE CSET calc_done=DONE
@@ -79,9 +83,9 @@ CSET clkout3_requested_phase=0.000
CSET clkout3_used=true CSET clkout3_used=true
CSET clkout4_drives=BUFG CSET clkout4_drives=BUFG
CSET clkout4_requested_duty_cycle=50.000 CSET clkout4_requested_duty_cycle=50.000
CSET clkout4_requested_out_freq=100.000 CSET clkout4_requested_out_freq=62.500
CSET clkout4_requested_phase=0.000 CSET clkout4_requested_phase=0.000
CSET clkout4_used=false CSET clkout4_used=true
CSET clkout5_drives=BUFG CSET clkout5_drives=BUFG
CSET clkout5_requested_duty_cycle=50.000 CSET clkout5_requested_duty_cycle=50.000
CSET clkout5_requested_out_freq=100.000 CSET clkout5_requested_out_freq=100.000
@@ -114,6 +118,7 @@ CSET dcm_clkfx_multiply=4
CSET dcm_clkgen_clk_out1_port=CLKFX CSET dcm_clkgen_clk_out1_port=CLKFX
CSET dcm_clkgen_clk_out2_port=CLKFX CSET dcm_clkgen_clk_out2_port=CLKFX
CSET dcm_clkgen_clk_out3_port=CLKFX CSET dcm_clkgen_clk_out3_port=CLKFX
CSET dcm_clkgen_clk_out4_port=CLKDV
CSET dcm_clkgen_clkfx_divide=1 CSET dcm_clkgen_clkfx_divide=1
CSET dcm_clkgen_clkfx_md_max=0.000 CSET dcm_clkgen_clkfx_md_max=0.000
CSET dcm_clkgen_clkfx_multiply=4 CSET dcm_clkgen_clkfx_multiply=4
@@ -165,7 +170,7 @@ CSET mmcm_clkout3_duty_cycle=0.500
CSET mmcm_clkout3_phase=0.000 CSET mmcm_clkout3_phase=0.000
CSET mmcm_clkout3_use_fine_ps=false CSET mmcm_clkout3_use_fine_ps=false
CSET mmcm_clkout4_cascade=false CSET mmcm_clkout4_cascade=false
CSET mmcm_clkout4_divide=1 CSET mmcm_clkout4_divide=2
CSET mmcm_clkout4_duty_cycle=0.500 CSET mmcm_clkout4_duty_cycle=0.500
CSET mmcm_clkout4_phase=0.000 CSET mmcm_clkout4_phase=0.000
CSET mmcm_clkout4_use_fine_ps=false CSET mmcm_clkout4_use_fine_ps=false
@@ -207,7 +212,7 @@ CSET pll_clkout2_phase=0.000
CSET pll_clkout3_divide=1 CSET pll_clkout3_divide=1
CSET pll_clkout3_duty_cycle=0.500 CSET pll_clkout3_duty_cycle=0.500
CSET pll_clkout3_phase=0.000 CSET pll_clkout3_phase=0.000
CSET pll_clkout4_divide=1 CSET pll_clkout4_divide=2
CSET pll_clkout4_duty_cycle=0.500 CSET pll_clkout4_duty_cycle=0.500
CSET pll_clkout4_phase=0.000 CSET pll_clkout4_phase=0.000
CSET pll_clkout5_divide=1 CSET pll_clkout5_divide=1
@@ -253,4 +258,4 @@ CSET use_spread_spectrum=false
CSET use_status=false CSET use_status=false
# END Parameters # END Parameters
GENERATE GENERATE
# CRC: 681ed89a # CRC: 42b0e01c

121
fpga/top/UmTRX/Makefile.UmTRXv2_nosram Normal file
View File

@@ -0,0 +1,121 @@
#
# Copyright 2012 Fairwaves
#
##################################################
# Project Setup
##################################################
TOP_MODULE = u2plus_umtrx_v2
BUILD_DIR = $(abspath build$(ISE)_UmTRXv2_nosram)
##################################################
# Include other makefiles
##################################################
include ../Makefile.common
include ../../fifo/Makefile.srcs
include ../../control_lib/Makefile.srcs
include ../../sdr_lib/Makefile.srcs
include ../../serdes/Makefile.srcs
include ../../simple_gemac/Makefile.srcs
include ../../timing/Makefile.srcs
include ../../opencores/Makefile.srcs
include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
include ../../gpsdo/Makefile.srcs
##################################################
# Project Properties
##################################################
export PROJECT_PROPERTIES := \
family "Spartan6" \
device xc6slx75 \
package fgg484 \
speed -2 \
top_level_module_type "HDL" \
synthesis_tool "XST (VHDL/Verilog)" \
simulator "ISE Simulator (VHDL/Verilog)" \
"Preferred Language" "Verilog" \
"Enable Message Filtering" FALSE \
"Display Incremental Messages" FALSE
##################################################
# Sources
##################################################
TOP_SRCS = \
capture_ddrlvds.v \
umtrx_core.v \
umtrx_tx_chain.v \
umtrx_rx_chain.v \
umtrx_router.v \
umtrx_packet_dispatcher.v \
coregen/chipscope_icon.v \
coregen/chipscope_icon.xco \
coregen/chipscope_ila.v \
coregen/chipscope_ila.xco \
coregen/fifo_short_2clk.v \
coregen/fifo_short_2clk.xco \
coregen/fifo_4k_2clk.v \
coregen/fifo_4k_2clk.xco \
coregen/fifo_axi_36.v \
coregen/fifo_axi_36.xco \
u2plus_umtrx_v2.v \
u2plus_umtrx_v2.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
$(GPSDO_SRCS)
##################################################
# Process Properties
##################################################
SYNTHESIZE_PROPERTIES = \
"Number of Clock Buffers" 8 \
"Pack I/O Registers into IOBs" Yes \
"Optimization Effort" High \
"Optimize Instantiated Primitives" TRUE \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
"Use Synchronous Set" Auto \
"Verilog Macros" "LVDS=1 | NO_SERDES=1 | UMTRX=1 | LMS602D_FRONTEND=1 | SPARTAN6=1 | LMS_DSP=1 | NUMDDC=2 | NUMDUC=2 | NO_EXT_FIFO=1 | INTERNAL_FIFOS=1"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
MAP_PROPERTIES = \
"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Global Optimization" Speed\
"Optimization Strategy (Cover Mode)" Speed \
"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
"Perform Timing-Driven Packing and Placement" TRUE \
"Map Effort Level" High \
"Extra Effort" Normal \
"Combinatorial Logic Optimization" TRUE \
"Register Duplication" TRUE
PLACE_ROUTE_PROPERTIES = \
"Place & Route Effort Level (Overall)" High \
"Place & Route Extra Effort (Highest PAR level only)" NORMAL
STATIC_TIMING_PROPERTIES = \
"Number of Paths in Error/Verbose Report" 10 \
"Report Type" "Error Report"
GEN_PROG_FILE_PROPERTIES = \
"Configuration Rate" 6 \
"Create Binary Configuration File" TRUE \
"Done (Output Events)" 5 \
"Enable Bitstream Compression" TRUE \
"Enable Outputs (Output Events)" 6
SIM_MODEL_PROPERTIES = ""

52
fpga/top/UmTRX/coregen/fifo_axi_36.gise Normal file
View File

@@ -0,0 +1,52 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_axi_36.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_axi_36.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_axi_36.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1501582277" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1501582277">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1501588912" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8970095556748691462" xil_pn:start_ts="1501588912">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1501588912" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1830686490926110834" xil_pn:start_ts="1501588912">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1501588912" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1501588912">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1501588912" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5214082714422500266" xil_pn:start_ts="1501588912">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>

491
fpga/top/UmTRX/coregen/fifo_axi_36.v Normal file
View File

@@ -0,0 +1,491 @@
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file fifo_axi_36.v when simulating
// the core, fifo_axi_36. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module fifo_axi_36(
m_aclk,
s_aclk,
s_aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tuser
);
input m_aclk;
input s_aclk;
input s_aresetn;
input s_axis_tvalid;
output s_axis_tready;
input [31 : 0] s_axis_tdata;
input [3 : 0] s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [31 : 0] m_axis_tdata;
output [3 : 0] m_axis_tuser;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(32),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DIN_WIDTH_AXIS(36),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(11),
.C_IMPLEMENTATION_TYPE_RACH(12),
.C_IMPLEMENTATION_TYPE_RDCH(11),
.C_IMPLEMENTATION_TYPE_WACH(12),
.C_IMPLEMENTATION_TYPE_WDCH(11),
.C_IMPLEMENTATION_TYPE_WRCH(12),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(1),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(32765),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(32767),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(32768),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(15),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.M_ACLK(m_aclk),
.S_ACLK(s_aclk),
.S_ARESETN(s_aresetn),
.S_AXIS_TVALID(s_axis_tvalid),
.S_AXIS_TREADY(s_axis_tready),
.S_AXIS_TDATA(s_axis_tdata),
.S_AXIS_TUSER(s_axis_tuser),
.M_AXIS_TVALID(m_axis_tvalid),
.M_AXIS_TREADY(m_axis_tready),
.M_AXIS_TDATA(m_axis_tdata),
.M_AXIS_TUSER(m_axis_tuser),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.RST(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.DIN(),
.WR_EN(),
.RD_EN(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.DOUT(),
.FULL(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.EMPTY(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule

213
fpga/top/UmTRX/coregen/fifo_axi_36.xco Normal file
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@@ -0,0 +1,213 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Tue Aug 1 09:18:38 2017
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx75
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Independent_Clock
CSET component_name=fifo_axi_36
CSET data_count=false
CSET data_count_width=10
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_assert_value_axis=32765
CSET empty_threshold_assert_value_rach=13
CSET empty_threshold_assert_value_rdch=1021
CSET empty_threshold_assert_value_wach=13
CSET empty_threshold_assert_value_wdch=1021
CSET empty_threshold_assert_value_wrch=13
CSET empty_threshold_negate_value=3
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=true
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=true
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation_axis=Independent_Clocks_Block_RAM
CSET fifo_implementation_rach=Independent_Clocks_Distributed_RAM
CSET fifo_implementation_rdch=Independent_Clocks_Block_RAM
CSET fifo_implementation_wach=Independent_Clocks_Distributed_RAM
CSET fifo_implementation_wdch=Independent_Clocks_Block_RAM
CSET fifo_implementation_wrch=Independent_Clocks_Distributed_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=1022
CSET full_threshold_assert_value_axis=32767
CSET full_threshold_assert_value_rach=15
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=15
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=15
CSET full_threshold_negate_value=1021
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=18
CSET input_depth=1024
CSET input_depth_axis=32768
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=AXI4
CSET output_data_width=18
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=32
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: ef6b9ccd

73
fpga/top/UmTRX/coregen/fifo_axi_36.xise Normal file
View File

@@ -0,0 +1,73 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_axi_36.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="fifo_axi_36.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_axi_36" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="fifo_axi_36.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_axi_36" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_axi_36" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-08-01T12:21:22" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3A42A837D86A509961F66E126F05239A" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

23
fpga/top/UmTRX/u2plus_umtrx_v2.v
View File

@@ -216,15 +216,18 @@ wire DivSw1, DivSw2;
// Status and control signals // Status and control signals
.LOCKED_OUT(led_stat)); // OUT .LOCKED_OUT(led_stat)); // OUT
wire clk_rx_div2;
pll_rx pll_rx_instance pll_rx pll_rx_instance
(// Clock in ports (// Clock in ports
.gmii_rx_clk(GMII_RX_CLK), // IN .gmii_rx_clk(GMII_RX_CLK), // IN
// Clock out ports // Clock out ports
.clk_rx(clk_rx), // OUT .clk_rx(clk_rx), // OUT
.clk_to_mac(CLK_TO_MAC_int2), // OUT .clk_to_mac(CLK_TO_MAC_int2), // OUT
.clk_rx_180(clk_rx_180)); // OUT .clk_rx_180(clk_rx_180),
.clk_rx_div2(clk_rx_div2)); // OUT
`ifndef NO_EXT_FIFO
OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK),
.C0(clk270_100_buf), .C0(clk270_100_buf),
.C1(~clk270_100_buf), .C1(~clk270_100_buf),
@@ -233,7 +236,17 @@ wire DivSw1, DivSw2;
.D1(1'b0), .D1(1'b0),
.R(1'b0), .R(1'b0),
.S(1'b0)); .S(1'b0));
`else
assign RAM_A = 0;
assign RAM_BWn = ~0;
assign RAM_ZZ = 1;
assign RAM_LDn = 1;
assign RAM_OEn = 1;
assign RAM_WEn = 1;
assign RAM_CENn = 1;
assign RAM_CLK = 1;
`endif
// I2C -- Don't use external transistors for open drain, the FPGA implements this // I2C -- Don't use external transistors for open drain, the FPGA implements this
IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
@@ -276,7 +289,7 @@ wire DivSw1, DivSw2;
.R(0), // Synchronous reset input .R(0), // Synchronous reset input
.S(0) // Synchronous preset input .S(0) // Synchronous preset input
); );
// //
// Instantiate IO for Bidirectional bus to SRAM // Instantiate IO for Bidirectional bus to SRAM
@@ -335,7 +348,7 @@ wire DivSw1, DivSw2;
end end
umtrx_core u2p_c( umtrx_core u2p_c(
.sys_clk (dsp_clk), .sys_clk (clk_rx_div2),
.dsp_clk (lms_clk), .dsp_clk (lms_clk),
.fe_clk (clk_icap), //1/2 dsp rate .fe_clk (clk_icap), //1/2 dsp rate
.wb_clk (wb_clk), .wb_clk (wb_clk),

98
fpga/top/UmTRX/umtrx_core.v
View File

@@ -624,8 +624,13 @@ module umtrx_core
(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sfc_clear)); (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sfc_clear));
wire sram_clear; wire sram_clear;
`ifdef INTERNAL_FIFOS
setting_reg #(.my_addr(SR_MISC+2),.width(1)) sr_sram_clear
(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sram_clear));
`else
setting_reg #(.my_addr(SR_MISC+2),.width(1)) sr_sram_clear setting_reg #(.my_addr(SR_MISC+2),.width(1)) sr_sram_clear
(.clk(sys_clk),.rst(sys_rst),.strobe(set_stb_sys),.addr(set_addr_sys),.in(set_data_sys),.changed(sram_clear)); (.clk(sys_clk),.rst(sys_rst),.strobe(set_stb_sys),.addr(set_addr_sys),.in(set_data_sys),.changed(sram_clear));
`endif
setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out(phy_reset),.changed()); (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out(phy_reset),.changed());
@@ -896,10 +901,15 @@ module umtrx_core
); );
// ///////////////////////////////////////////////////////////////////////// // /////////////////////////////////////////////////////////////////////////
// TX chains // TX chains
wire [35:0] sram0_data, sram1_data; wire [35:0] vita0_data_dsp;
wire sram0_valid, sram1_valid; wire vita0_valid_dsp;
wire sram0_ready, sram1_ready; wire vita0_ready_dsp;
wire [35:0] vita1_data_dsp;
wire vita1_valid_dsp;
wire vita1_ready_dsp;
wire run_tx_dsp0, run_tx_dsp1; wire run_tx_dsp0, run_tx_dsp1;
//switch to select frontend used per DSP //switch to select frontend used per DSP
@@ -931,12 +941,12 @@ module umtrx_core
.set_stb_dsp(set_stb_dsp), .set_addr_dsp(set_addr_dsp), .set_data_dsp(set_data_dsp), .set_stb_dsp(set_stb_dsp), .set_addr_dsp(set_addr_dsp), .set_data_dsp(set_data_dsp),
.set_stb_fe(set_stb_fe), .set_addr_fe(set_addr_fe), .set_data_fe(set_data_fe), .set_stb_fe(set_stb_fe), .set_addr_fe(set_addr_fe), .set_data_fe(set_data_fe),
.front_i(dac0_a_int), .front_q(dac0_b_int), .dac_stb(dac0_strobe), .run(run_tx_dsp0), .front_i(dac0_a_int), .front_q(dac0_b_int), .dac_stb(dac0_strobe), .run(run_tx_dsp0),
.vita_data_sys(sram0_data), .vita_valid_sys(sram0_valid), .vita_ready_sys(sram0_ready), .vita_data_dsp(vita0_data_dsp), .vita_valid_dsp(vita0_valid_dsp), .vita_ready_dsp(vita0_ready_dsp),
.err_data_sys(err_tx0_data), .err_valid_sys(err_tx0_valid), .err_ready_sys(err_tx0_ready), .err_data_sys(err_tx0_data), .err_valid_sys(err_tx0_valid), .err_ready_sys(err_tx0_ready),
.vita_time(vita_time) .vita_time(vita_time)
); );
end else begin end else begin
assign sram0_ready = 1; assign vita0_ready_dsp = 1;
assign err_tx0_valid = 0; assign err_tx0_valid = 0;
assign run_tx_dsp0 = 0; assign run_tx_dsp0 = 0;
end end
@@ -957,12 +967,12 @@ module umtrx_core
.set_stb_dsp(set_stb_dsp), .set_addr_dsp(set_addr_dsp), .set_data_dsp(set_data_dsp), .set_stb_dsp(set_stb_dsp), .set_addr_dsp(set_addr_dsp), .set_data_dsp(set_data_dsp),
.set_stb_fe(set_stb_fe), .set_addr_fe(set_addr_fe), .set_data_fe(set_data_fe), .set_stb_fe(set_stb_fe), .set_addr_fe(set_addr_fe), .set_data_fe(set_data_fe),
.front_i(dac1_a_int), .front_q(dac1_b_int), .dac_stb(dac1_strobe), .run(run_tx_dsp1), .front_i(dac1_a_int), .front_q(dac1_b_int), .dac_stb(dac1_strobe), .run(run_tx_dsp1),
.vita_data_sys(sram1_data), .vita_valid_sys(sram1_valid), .vita_ready_sys(sram1_ready), .vita_data_dsp(vita1_data_dsp), .vita_valid_dsp(vita1_valid_dsp), .vita_ready_dsp(vita1_ready_dsp),
.err_data_sys(err_tx1_data), .err_valid_sys(err_tx1_valid), .err_ready_sys(err_tx1_ready), .err_data_sys(err_tx1_data), .err_valid_sys(err_tx1_valid), .err_ready_sys(err_tx1_ready),
.vita_time(vita_time) .vita_time(vita_time)
); );
end else begin end else begin
assign sram1_ready = 1; assign vita1_ready_dsp = 1;
assign err_tx1_valid = 0; assign err_tx1_valid = 0;
assign run_tx_dsp1 = 0; assign run_tx_dsp1 = 0;
end end
@@ -986,6 +996,77 @@ module umtrx_core
// /////////////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////////////
// DSP TX // DSP TX
//`define INTERNAL_FIFOS
`ifdef INTERNAL_FIFOS
wire [35:0] vita0_data_cc;
wire [35:0] vita1_data_cc;
wire vita0_valid_cc, vita1_valid_cc;
wire vita0_ready_cc, vita1_ready_cc;
axi_fifo_2clk #(.WIDTH(36), .SIZE(9)) fifo_tx0_sys_dsp
(
.i_aclk(sys_clk), .i_tdata(dsp_tx0_data), .i_tvalid(dsp_tx0_valid), .i_tready(dsp_tx0_ready),
.o_aclk(dsp_clk), .o_tdata(vita0_data_cc), .o_tvalid(vita0_valid_cc), .o_tready(vita0_ready_cc),
.reset(dsp_rst | sys_rst | sram_clear)
);
axi_fifo_2clk #(.WIDTH(36), .SIZE(9)) fifo_tx1_sys_dsp
(
.i_aclk(sys_clk), .i_tdata(dsp_tx1_data), .i_tvalid(dsp_tx1_valid), .i_tready(dsp_tx1_ready),
.o_aclk(dsp_clk), .o_tdata(vita1_data_cc), .o_tvalid(vita1_valid_cc), .o_tready(vita1_ready_cc),
.reset(dsp_rst | sys_rst | sram_clear)
);
fifo_axi_36 ififo0(
.s_aclk(dsp_clk),
.s_aresetn(~((dsp_rst | sram_clear))),
.s_axis_tvalid(vita0_valid_cc),
.s_axis_tready(vita0_ready_cc),
.s_axis_tdata(vita0_data_cc[31:0]),
.s_axis_tuser(vita0_data_cc[35:32]),
.m_aclk(dsp_clk),
.m_axis_tvalid(vita0_valid_dsp),
.m_axis_tready(vita0_ready_dsp),
.m_axis_tdata(vita0_data_dsp[31:0]),
.m_axis_tuser(vita0_data_dsp[35:32])
);
fifo_axi_36 ififo1(
.s_aclk(dsp_clk),
.s_aresetn(~((dsp_rst | sram_clear))),
.s_axis_tvalid(vita1_valid_cc),
.s_axis_tready(vita1_ready_cc),
.s_axis_tdata(vita1_data_cc[31:0]),
.s_axis_tuser(vita1_data_cc[35:32]),
.m_aclk(dsp_clk),
.m_axis_tvalid(vita1_valid_dsp),
.m_axis_tready(vita1_ready_dsp),
.m_axis_tdata(vita1_data_dsp[31:0]),
.m_axis_tuser(vita1_data_dsp[35:32])
);
`else
wire [35:0] sram0_data, sram1_data;
wire sram0_valid, sram1_valid;
wire sram0_ready, sram1_ready;
axi_fifo_2clk #(.WIDTH(36), .SIZE(0)) fifo_tx0_2clock_vita
(
.i_aclk(sys_clk), .i_tdata(sram0_data), .i_tvalid(sram0_valid), .i_tready(sram0_ready),
.o_aclk(dsp_clk), .o_tdata(vita0_data_dsp), .o_tvalid(vita0_valid_dsp), .o_tready(vita0_ready_dsp),
.reset(dsp_rst | sys_rst)
);
axi_fifo_2clk #(.WIDTH(36), .SIZE(0)) fifo_tx1_2clock_vita
(
.i_aclk(sys_clk), .i_tdata(sram1_data), .i_tvalid(sram1_valid), .i_tready(sram1_ready),
.o_aclk(dsp_clk), .o_tdata(vita1_data_dsp), .o_tvalid(vita1_valid_dsp), .o_tready(vita1_ready_dsp),
.reset(dsp_rst | sys_rst)
);
`ifndef NO_EXT_FIFO `ifndef NO_EXT_FIFO
assign RAM_A[20:19] = 2'b0; assign RAM_A[20:19] = 2'b0;
@@ -1030,6 +1111,7 @@ module umtrx_core
.dataout_1(sram1_data), .dataout_1(sram1_data),
.debug(debug_extfifo), .debug(debug_extfifo),
.debug2(debug_extfifo2) ); .debug2(debug_extfifo2) );
`endif
// ///////////////////////////////////////////////////////////////////////// // /////////////////////////////////////////////////////////////////////////
// VITA Timing // VITA Timing

22
fpga/top/UmTRX/umtrx_tx_chain.v
View File

@@ -37,10 +37,10 @@ module umtrx_tx_chain
input dac_stb, input dac_stb,
output run, output run,
//sys clock domain //dsp clock domain
input [35:0] vita_data_sys, input [35:0] vita_data_dsp,
input vita_valid_sys, input vita_valid_dsp,
output vita_ready_sys, output vita_ready_dsp,
//sys clock domain //sys clock domain
output [35:0] err_data_sys, output [35:0] err_data_sys,
@@ -91,9 +91,15 @@ module umtrx_tx_chain
/******************************************************************* /*******************************************************************
* TX VITA deframer * TX VITA deframer
******************************************************************/ ******************************************************************/
wire [35:0] vita_data_dsp, err_data_dsp; /*
wire vita_valid_dsp, err_valid_dsp; wire [35:0] vita_data_dsp;
wire vita_ready_dsp, err_ready_dsp; wire vita_valid_dsp;
wire vita_ready_dsp;
*/
wire [35:0] err_data_dsp;
wire err_valid_dsp;
wire err_ready_dsp;
vita_tx_chain #(.BASE(CTRL_BASE), .UNIT(PROT_DEST), .FIFOSIZE(FIFOSIZE), vita_tx_chain #(.BASE(CTRL_BASE), .UNIT(PROT_DEST), .FIFOSIZE(FIFOSIZE),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(1), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
@@ -114,12 +120,14 @@ module umtrx_tx_chain
/******************************************************************* /*******************************************************************
* Cross clock fifo from sys to dsp clock domain * Cross clock fifo from sys to dsp clock domain
******************************************************************/ ******************************************************************/
/*
axi_fifo_2clk #(.WIDTH(36), .SIZE(0)) fifo_2clock_vita axi_fifo_2clk #(.WIDTH(36), .SIZE(0)) fifo_2clock_vita
( (
.i_aclk(sys_clk), .i_tdata(vita_data_sys), .i_tvalid(vita_valid_sys), .i_tready(vita_ready_sys), .i_aclk(sys_clk), .i_tdata(vita_data_sys), .i_tvalid(vita_valid_sys), .i_tready(vita_ready_sys),
.o_aclk(dsp_clk), .o_tdata(vita_data_dsp), .o_tvalid(vita_valid_dsp), .o_tready(vita_ready_dsp), .o_aclk(dsp_clk), .o_tdata(vita_data_dsp), .o_tvalid(vita_valid_dsp), .o_tready(vita_ready_dsp),
.reset(dsp_rst | sys_rst) .reset(dsp_rst | sys_rst)
); );
*/
axi_fifo_2clk #(.WIDTH(36), .SIZE(0)) fifo_2clock_err axi_fifo_2clk #(.WIDTH(36), .SIZE(0)) fifo_2clock_err
( (
.i_aclk(dsp_clk), .i_tdata(err_data_dsp), .i_tvalid(err_valid_dsp), .i_tready(err_ready_dsp), .i_aclk(dsp_clk), .i_tdata(err_data_dsp), .i_tvalid(err_valid_dsp), .i_tready(err_ready_dsp),