host: Check if DC offset value reads as it's been written to LMS.

We had an issue with GPS 1pps signals disrupting SPI operations,
which was mostly visible during calibratoin, because it takes
many SPI operations to finish. And because the key operation
during calibration is DC offset altering, it's easy to spot when
SPI is working incorrectrly by checking it. It's a useless check
in a normal situation, so I don't want to see this in production
code.

debian/changelog

@@ -1,3 +1,25 @@
+umtrx (1.0.6) trusty; urgency=low
+
+  * host: make boost property tree thread safe
+  * host: support string type in JSON query
+  * debian: build now produces an additional package with debug symbols
+  * umtrx_firmware: fixed typo preventing it from working
+
+ -- Kirill Zakharenko <earwin@gmail.com>  Mon, 21 Dec 2015 14:23:56 +0300
+
+umtrx (1.0.5) trusty; urgency=low
+
+  * host: disable umtrx_fifo_ctrl cache of spi config
+  * host: Fix getters in umtrx_property_tree.py.
+  * debian: added firmware to package and umtrx_firmware script to handle it
+  * fpga: created axi stream controled spi core
+  * fpga: use axi stream spi core (still single dest)
+  * fpga: connect both spi settings drivers
+  * fpga: simplify spi setting regs with generate loop
+  * fpga: updated 4x ddc image for spi work
+
+ -- Kirill Zakharenko <earwin@gmail.com>  Mon, 23 Nov 2015 15:51:56 +0300
+
 umtrx (1.0.4) unstable; urgency=low
 
   * Do not add 'g' to a git id when creating a version string.

debian/control

@@ -31,3 +31,10 @@ Conflicts: umtrx-uhd
 Replaces: umtrx-uhd
 Description: Fairwaves UmTRX driver - UHD plugin module
  The industrial grade dual-channel wide-band SDR transceiver.
+
+Package: umtrx-dbg
+Section: debug
+Architecture: any
+Depends: umtrx, uhd-umtrx, ${misc:Depends}
+Description: Fairwaves UmTRX driver - debug symbols
+ The industrial grade dual-channel wide-band SDR transceiver.

debian/rules

@@ -16,3 +16,6 @@ export DH_OPTIONS
 
 override_dh_auto_configure:
 	dh_auto_configure -- -DLIB_SUFFIX="/$(DEB_HOST_MULTIARCH)"
+
+override_dh_strip:
+	dh_strip --dbg-package=umtrx-dbg

debian/umtrx.install

@@ -1 +1,2 @@
 usr/bin
+images/u2plus_umtrx_v2.bin images/umtrx_txrx_uhd.bin usr/share/umtrx/firmware

fpga/control_lib/Makefile.srcs

@@ -58,5 +58,6 @@ gpio_atr.v \
 user_settings.v \
 settings_fifo_ctrl.v \
 simple_spi_core.v \
+axis_spi_core.v \
 simple_i2c_core.v \
 ))

fpga/control_lib/axis_spi_core.v

@@ -0,0 +1,243 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// Simple SPI core, the simplest, yet complete spi core I can think of
+
+// Settings register controlled.
+// 2 settings regs, control and data
+// 1 32-bit readback and status signal
+
+// Settings reg map:
+//
+// BASE+0 divider setting
+// bits [15:0] spi clock divider
+//
+// BASE+1 configuration input
+// bits [23:0] slave select, bit0 = slave0 enabled
+// bits [29:24] num bits (1 through 32)
+// bit [30] data input edge = in data bit latched on rising edge of clock
+// bit [31] data output edge = out data bit latched on rising edge of clock
+//
+// BASE+2 input data
+// Writing this register begins a spi transaction.
+// Bits are latched out from bit 0.
+// Therefore, load this register in reverse.
+//
+// Readback
+// Bits are latched into bit 0.
+// Therefore, data will be in-order.
+
+module axis_spi_core
+    #(
+        //set to 1 for ILA
+        parameter DEBUG = 0,
+
+        //tdest width for number of core users
+        parameter DESTW = 1,
+
+        //width of serial enables (up to 24 is possible)
+        parameter WIDTH = 8,
+
+        //idle state of the spi clock
+        parameter CLK_IDLE = 0,
+
+        //idle state of the serial enables
+        parameter SEN_IDLE = 24'hffffff
+    )
+    (
+        //clock and synchronous reset
+        input clock, input reset,
+
+        //configuration settings bus
+        input [DESTW-1:0] CONFIG_tdest,
+        input [79:0] CONFIG_tdata,
+        input CONFIG_tvalid,
+        output CONFIG_tready,
+
+        //32-bit data readback
+        output reg [DESTW-1:0] READBACK_tdest,
+        output [31:0] READBACK_tdata,
+        output READBACK_tvalid,
+        input READBACK_tready,
+
+        //spi interface, slave selects, clock, data in, data out
+        output [WIDTH-1:0] sen,
+        output sclk,
+        output mosi,
+        input miso
+    );
+
+    //state
+    localparam WAIT_CONFIG = 0;
+    localparam PRE_IDLE = 1;
+    localparam CLK_REG = 2;
+    localparam CLK_INV = 3;
+    localparam POST_IDLE = 4;
+    localparam IDLE_SEN = 5;
+    localparam WAIT_READBACK = 6;
+    reg [2:0] state;
+
+    //configuration settings
+    reg [15:0] sclk_divider;
+    reg [23:0] slave_select;
+    reg [5:0] num_bits;
+    reg datain_edge, dataout_edge;
+
+    //output ready/valid signals
+    assign CONFIG_tready = (state == WAIT_CONFIG);
+    assign READBACK_tvalid = (state == WAIT_READBACK);
+
+    //serial clock either idles or is in one of two clock states
+    reg sclk_reg;
+    assign sclk = sclk_reg;
+
+    //serial enables either idle or enabled based on state
+    wire sen_is_idle = (state == WAIT_CONFIG) || (state == IDLE_SEN);
+    wire [23:0] sen24 = (sen_is_idle)? SEN_IDLE : (SEN_IDLE ^ slave_select);
+    reg [WIDTH-1:0] sen_reg;
+    always @(posedge clock) sen_reg <= sen24[WIDTH-1:0];
+    assign sen = sen_reg;
+
+    //data output shift register
+    reg [31:0] dataout_reg;
+    wire [31:0] dataout_next = {dataout_reg[30:0], 1'b0};
+    assign mosi = dataout_reg[31];
+
+    //data input shift register
+    reg [31:0] datain_reg;
+    wire [31:0] datain_next = {datain_reg[30:0], miso};
+    assign READBACK_tdata = datain_reg;
+
+    //counter for spi clock
+    reg [15:0] sclk_counter;
+    wire sclk_counter_done = (sclk_counter == sclk_divider);
+    wire [15:0] sclk_counter_next = (sclk_counter_done)? 0 : sclk_counter + 1;
+
+    //counter for latching bits miso/mosi
+    reg [6:0] bit_counter;
+    wire [6:0] bit_counter_next = bit_counter + 1;
+    wire bit_counter_done = (bit_counter_next == num_bits);
+
+    always @(posedge clock) begin
+        if (reset) begin
+            state <= WAIT_CONFIG;
+            sclk_reg <= CLK_IDLE;
+        end
+        else begin
+            case (state)
+
+            WAIT_CONFIG: begin
+                if (CONFIG_tvalid && CONFIG_tready) begin
+                    state <= PRE_IDLE;
+                end
+                {sclk_divider, dataout_edge, datain_edge, num_bits, slave_select, dataout_reg} <= CONFIG_tdata;
+                READBACK_tdest <= CONFIG_tdest;
+                sclk_counter <= 0;
+                bit_counter <= 0;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            PRE_IDLE: begin
+                if (sclk_counter_done) state <= CLK_REG;
+                sclk_counter <= sclk_counter_next;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            CLK_REG: begin
+                if (sclk_counter_done) begin
+                    state <= CLK_INV;
+                    if (datain_edge  != CLK_IDLE)                     datain_reg  <= datain_next;
+                    if (dataout_edge != CLK_IDLE && bit_counter != 0) dataout_reg <= dataout_next;
+                    sclk_reg <= ~CLK_IDLE; //transition to rising when CLK_IDLE == 0
+                end
+                sclk_counter <= sclk_counter_next;
+            end
+
+            CLK_INV: begin
+                if (sclk_counter_done) begin
+                    state <= (bit_counter_done)? POST_IDLE : CLK_REG;
+                    bit_counter <= bit_counter_next;
+                    if (datain_edge  == CLK_IDLE)                      datain_reg  <= datain_next;
+                    if (dataout_edge == CLK_IDLE && ~bit_counter_done) dataout_reg <= dataout_next;
+                    sclk_reg <= CLK_IDLE; //transition to falling when CLK_IDLE == 0
+                end
+                sclk_counter <= sclk_counter_next;
+            end
+
+            POST_IDLE: begin
+                if (sclk_counter_done) state <= IDLE_SEN;
+                sclk_counter <= sclk_counter_next;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            IDLE_SEN: begin
+                if (sclk_counter_done) state <= WAIT_READBACK;
+                sclk_counter <= sclk_counter_next;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            WAIT_READBACK: begin
+                if (READBACK_tready && READBACK_tvalid) begin
+                    state <= WAIT_CONFIG;
+                end
+            end
+
+            default: state <= WAIT_CONFIG;
+
+            endcase //state
+        end
+    end
+
+    /*******************************************************************
+     * Debug
+     ******************************************************************/
+    generate
+    if (DEBUG == 1) begin
+        wire [35:0] CONTROL0;
+        chipscope_icon chipscope_icon
+        (
+            .CONTROL0(CONTROL0)
+        );
+        wire [255:0] DATA;
+        wire [7:0] TRIG0;
+        chipscope_ila chipscope_ila
+        (
+            .CONTROL(CONTROL0),
+            .CLK(clock),
+            .DATA(DATA),
+            .TRIG0(TRIG0)
+        );
+        assign TRIG0 =
+        {
+            4'b0,
+            CONFIG_tvalid, CONFIG_tready,
+            READBACK_tvalid, READBACK_tready
+        };
+
+        assign DATA[79:0] = CONFIG_tdata;
+        assign DATA[111:80] = READBACK_tdata;
+
+        assign DATA[112] = CONFIG_tvalid;
+        assign DATA[113] = CONFIG_tready;
+        assign DATA[114] = READBACK_tvalid;
+        assign DATA[115] = READBACK_tready;
+
+        assign DATA[127:120] = state;
+    end
+    endgenerate
+
+endmodule //axis_spi_core

fpga/top/UmTRX/umtrx_core.v

@@ -174,6 +174,10 @@ module umtrx_core
    wire [7:0] 	set_addr, set_addr_dsp, set_addr_sys, set_addr_fe, set_addr_udp_wb, set_addr_udp_sys;
    wire [31:0] 	set_data, set_data_dsp, set_data_sys, set_data_fe, set_data_udp_wb, set_data_udp_sys;
    wire 	set_stb, set_stb_dsp, set_stb_sys, set_stb_fe, set_stb_udp_wb, set_stb_udp_sys;
+
+   wire set_stb_dsp0, set_stb_dsp1;
+   wire [31:0] set_data_dsp0, set_data_dsp1;
+   wire [7:0] set_addr_dsp0, set_addr_dsp1;
    
    reg 		wb_rst;
    wire 	dsp_rst, sys_rst, fe_rst;
@@ -412,17 +416,80 @@ module umtrx_core
 
    // /////////////////////////////////////////////////////////////////////////
    // SPI -- Slave #2
-    wire [31:0] spi_debug;
-    wire [31:0] spi_readback;
+    reg [31:0] spi_readback0;
+    reg [31:0] spi_readback1;
     wire spi_ready;
-    simple_spi_core #(.BASE(SR_SPI_CORE), .WIDTH(5)) shared_spi(
+
+    wire [0:0] AXIS_SPI_CONFIG_tdest;
+    wire [79:0] AXIS_SPI_CONFIG_tdata;
+    wire AXIS_SPI_CONFIG_tvalid;
+    wire AXIS_SPI_CONFIG_tready;
+
+    wire [0:0] AXIS_SPI_READBACK_tdest;
+    wire [31:0] AXIS_SPI_READBACK_tdata;
+    wire AXIS_SPI_READBACK_tvalid;
+    wire AXIS_SPI_READBACK_tready;
+
+    axis_spi_core #(.DESTW(1), .WIDTH(5), .DEBUG(0)) axis_shared_spi(
         .clock(dsp_clk), .reset(dsp_rst),
-        .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-        .readback(spi_readback), .ready(spi_ready),
+
+        .CONFIG_tdest(AXIS_SPI_CONFIG_tdest),
+        .CONFIG_tdata(AXIS_SPI_CONFIG_tdata),
+        .CONFIG_tvalid(AXIS_SPI_CONFIG_tvalid),
+        .CONFIG_tready(AXIS_SPI_CONFIG_tready),
+
+        .READBACK_tdest(AXIS_SPI_READBACK_tdest),
+        .READBACK_tdata(AXIS_SPI_READBACK_tdata),
+        .READBACK_tvalid(AXIS_SPI_READBACK_tvalid),
+        .READBACK_tready(AXIS_SPI_READBACK_tready),
+
         .sen({aux_sen2,aux_sen1,sen_dac,sen_lms2,sen_lms1}),
-        .sclk(sclk), .mosi(mosi), .miso(miso), .debug(spi_debug)
+        .sclk(sclk), .mosi(mosi), .miso(miso)
     );
 
+    //setting register block for spi dest 0 (wishbone) and spi dest 1 (ctrl fifo)
+    //Note: the strobes are exclusive (settings fifo cross clock)
+    wire [79:0] spi_config [0:1];
+    wire [0:1] spi_trigger;
+    wire [0:1] set_stb_dsp_n = {set_stb_dsp0, set_stb_dsp1};
+    genvar i;
+    generate for (i=0; i <= 1; i=i+1) begin
+        setting_reg #(.my_addr(SR_SPI_CORE+2),.width(32)) axis_shared_spi_sr0(
+            .clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp_n[i]),.addr(set_addr_dsp),.in(set_data_dsp),
+            .out(spi_config[i][31:0]),.changed(spi_trigger[i]));
+
+        setting_reg #(.my_addr(SR_SPI_CORE+1),.width(32)) axis_shared_spi_sr1(
+            .clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp_n[i]),.addr(set_addr_dsp),.in(set_data_dsp),
+            .out(spi_config[i][63:32]),.changed());
+
+        setting_reg #(.my_addr(SR_SPI_CORE+0),.width(16)) axis_shared_spi_sr2(
+            .clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp_n[i]),.addr(set_addr_dsp),.in(set_data_dsp),
+            .out(spi_config[i][79:64]),.changed());
+    end endgenerate
+
+    //assign config bus from setting register sources
+    //Note: the triggers are exclusive (settings fifo cross clock)
+    assign AXIS_SPI_CONFIG_tdest = (spi_trigger[0])?1'b0:1'b1;
+    assign AXIS_SPI_CONFIG_tdata = (spi_trigger[0])?spi_config[0]:spi_config[1];
+    assign AXIS_SPI_CONFIG_tvalid = (spi_trigger != 0);
+
+    //create spi ready to block the ctrl fifo ASAP
+    wire spi_ready_now = AXIS_SPI_CONFIG_tready && !AXIS_SPI_CONFIG_tvalid;
+    assign spi_ready = spi_ready_now && spi_ready_prev;
+    reg spi_ready_prev;
+    always @(posedge dsp_clk) begin
+        spi_ready_prev <= spi_ready_now;
+    end
+
+    //readback output bus latches values into readback register
+    assign AXIS_SPI_READBACK_tready = 1'b1;
+    always @(posedge dsp_clk) begin
+        if (AXIS_SPI_READBACK_tvalid && AXIS_SPI_READBACK_tready) begin
+            if (AXIS_SPI_READBACK_tdest == 1'b0) spi_readback0 <= AXIS_SPI_READBACK_tdata;
+            if (AXIS_SPI_READBACK_tdest == 1'b1) spi_readback1 <= AXIS_SPI_READBACK_tdata;
+        end
+    end
+
    // /////////////////////////////////////////////////////////////////////////
    // I2C -- Slave #3
    i2c_master_top #(.ARST_LVL(1)) 
@@ -448,7 +515,7 @@ module umtrx_core
    // Buffer Pool Status -- Slave #5   
    
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd9, 16'd1}; //major, minor
+   localparam compat_num = {16'd9, 16'd2}; //major, minor
 
    wire [31:0] irq_readback = {16'b0, aux_ld2, aux_ld1, button, spi_ready, 12'b0};
 
@@ -456,7 +523,7 @@ module umtrx_core
      (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
       .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
 
-      .word00(spi_readback),.word01(`NUMDDC),.word02(`NUMDUC),.word03(32'b0),
+      .word00(spi_readback0),.word01(`NUMDDC),.word02(`NUMDUC),.word03(32'b0),
       .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
       .word08(status),.word09(32'b0),.word10(vita_time[63:32]),
       .word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback),
@@ -498,10 +565,6 @@ module umtrx_core
      (.clk_i(dsp_clk), .rst_i(dsp_rst), .set_stb_i(set_stb_dsp), .set_addr_i(set_addr_dsp), .set_data_i(set_data_dsp),
       .clk_o(fe_clk), .rst_o(fe_rst), .set_stb_o(set_stb_fe), .set_addr_o(set_addr_fe), .set_data_o(set_data_fe));
 
-   wire set_stb_dsp0, set_stb_dsp1;
-   wire [31:0] set_data_dsp0, set_data_dsp1;
-   wire [7:0] set_addr_dsp0, set_addr_dsp1;
-
    //mux settings_bus_crossclock and settings_readback_bus_fifo_ctrl with prio
    assign set_stb_dsp = set_stb_dsp0 | set_stb_dsp1;
    assign set_addr_dsp = set_stb_dsp1? set_addr_dsp1 : set_addr_dsp0;
@@ -542,7 +605,7 @@ module umtrx_core
         .in_data(ctrl_data_dsp), .in_valid(ctrl_valid_dsp), .in_ready(ctrl_ready_dsp),
         .out_data(resp_data_dsp), .out_valid(resp_valid_dsp), .out_ready(resp_ready_dsp),
         .strobe(set_stb_dsp1), .addr(set_addr_dsp1), .data(set_data_dsp1),
-        .word00(spi_readback),.word01(32'b0),.word02(32'b0),.word03(32'b0),
+        .word00(spi_readback1),.word01(32'b0),.word02(32'b0),.word03(32'b0),
         .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
         .word08(32'b0),.word09(32'b0),.word10(vita_time[63:32]),
         .word11(vita_time[31:0]),.word12(32'b0),.word13(irq_readback),

host/CMakeLists.txt

@@ -128,6 +128,10 @@ if (UNIX)
     list(APPEND UMTRX_LIBRARIES ${CMAKE_THREAD_LIBS_INIT})
 endif()
 
+#make boost property tree thread safe
+#http://stackoverflow.com/questions/8156948/is-boostproperty-treeptree-thread-safe
+add_definitions(-DBOOST_SPIRIT_THREADSAFE)
+
 ########################################################################
 # Helpful compiler flags
 ########################################################################

host/lms6002d_ctrl.cpp

@@ -395,6 +395,10 @@ protected:
         boost::recursive_mutex::scoped_lock l(_mutex);
         if (verbosity>0) printf("lms6002d_ctrl_impl::set_tx_vga1dc_i_int(%d)\n", offset);
         lms.set_tx_vga1dc_i_int(offset);
+        uint8_t old = lms.get_tx_vga1dc_i_int();
+        if (offset != old) {
+            lms.dump();
+        }
         return offset;
     }
 
@@ -402,6 +406,10 @@ protected:
         boost::recursive_mutex::scoped_lock l(_mutex);
         if (verbosity>0) printf("lms6002d_ctrl_impl::set_tx_vga1dc_q_int(%d)\n", offset);
         lms.set_tx_vga1dc_q_int(offset);
+        uint8_t old = lms.get_tx_vga1dc_q_int();
+        if (offset != old) {
+            lms.dump();
+        }
         return offset;
     }
 

host/umtrx_monitor.cpp

@@ -187,7 +187,8 @@ void umtrx_impl::client_query_handle1(const boost::property_tree::ptree &request
     else if (action == "GET")
     {
         const std::string type = request.get("type", "");
-        if (type.empty()) response.put("error", "type field not specified: BOOL, INT, DOUBLE, SENSOR, RANGE");
+        if (type.empty()) response.put("error", "type field not specified: STRING, BOOL, INT, DOUBLE, SENSOR, RANGE");
+        else if (type == "STRING") response.put("result", _tree->access<std::string>(path).get());
         else if (type == "BOOL") response.put("result", _tree->access<bool>(path).get());
         else if (type == "INT") response.put("result", _tree->access<int>(path).get());
         else if (type == "DOUBLE") response.put("result", _tree->access<double>(path).get());
@@ -218,7 +219,8 @@ void umtrx_impl::client_query_handle1(const boost::property_tree::ptree &request
     else if (action == "SET")
     {
         const std::string type = request.get("type", "");
-        if (type.empty()) response.put("error", "type field not specified: BOOL, INT, DOUBLE");
+        if (type.empty()) response.put("error", "type field not specified: STRING, BOOL, INT, DOUBLE");
+        else if (type == "STRING") _tree->access<std::string>(path).set(request.get<std::string>("value"));
         else if (type == "BOOL") _tree->access<bool>(path).set(request.get<bool>("value"));
         else if (type == "INT") _tree->access<int>(path).set(request.get<int>("value"));
         else if (type == "DOUBLE") _tree->access<double>(path).set(request.get<double>("value"));

host/utils/CMakeLists.txt

@@ -6,6 +6,7 @@ INSTALL(PROGRAMS
     umtrx_nmea
     umtrx_gps_coord
     umtrx_auto_calibration
+    umtrx_firmware
     DESTINATION bin
 )
 

host/utils/umtrx_firmware

@@ -0,0 +1,16 @@
+#!/bin/bash
+
+case $1 in
+    flash )
+        umtrx_net_burner --addr=192.168.10.2 --fpga=/usr/share/umtrx/firmware/u2plus_umtrx_v2.bin --fw=/usr/share/umtrx/firmware/umtrx_txrx_uhd.bin --reset
+        ;;
+    check )
+        ;;
+    * )
+        cat <<-EOF
+        Usage:
+        $0 flash  - burn packaged firmware to umtrx
+        $0 check  - compare versions of packaged firmware and one installed on umtrx
+EOF
+        ;;
+esac

host/utils/umtrx_property_tree.py

@@ -51,37 +51,45 @@ class umtrx_property_tree:
     self._send_request('GET', path, value_type='DOUBLE')
     return self._recv_response()
 
-  def query_sensor_raw(self, sensor_path):
-    self._send_request('GET', sensor_path, value_type='SENSOR')
+  def query_sensor_raw(self, path):
+    self._send_request('GET', path, value_type='SENSOR')
     return self._recv_response()
 
   def query_range_raw(self, path):
     self._send_request('GET', path, value_type='RANGE')
     return self._recv_response()
 
+  def query_string_raw(self, path):
+    self._send_request('GET', path, value_type='STRING')
+    return self._recv_response()
+
   #
   # Getters (value)
   #
 
   def query_bool_value(self, path):
-    res = self.query_bool_raw(sensor_path)
+    res = self.query_bool_raw(path)
     return res['result']['value']
 
   def query_int_value(self, path):
-    res = self.query_int_raw(sensor_path)
+    res = self.query_int_raw(path)
     return res['result']['value']
 
   def query_double_value(self, path):
-    res = self.query_double_raw(sensor_path)
+    res = self.query_double_raw(path)
     return res['result']['value']
 
-  def query_sensor_value(self, sensor_path):
-    res = self.query_sensor_raw(sensor_path)
+  def query_sensor_value(self, path):
+    res = self.query_sensor_raw(path)
     return res['result']['value']
 
   def query_range_value(self, path):
-    res = self.query_range_raw(sensor_path)
-    return res['result']['value']
+    res = self.query_range_raw(path)
+    return res['result']
+
+  def query_string_value(self, path):
+    res = self.query_string_raw(path)
+    return res['result']
 
   #
   # Setters
@@ -99,6 +107,10 @@ class umtrx_property_tree:
     self._send_request('SET', path, value_type='DOUBLE', value=val)
     return self._recv_response()
 
+  def set_string(self, path, val):
+    self._send_request('SET', path, value_type='STRING', value=val)
+    return self._recv_response()
+
   #
   # Check path presence and list paths
   #

host/utils/umtrx_query_versions.py

@@ -0,0 +1,20 @@
+#!/usr/bin/env python
+# -*- coding: utf-8 -*-
+
+##########################
+###  Query sensors
+##########################
+
+from umtrx_property_tree import umtrx_property_tree
+
+s = umtrx_property_tree()
+s.connect()
+
+mb_path="/mboards/0"
+fpga_version = s.query_string_value(mb_path+"/fpga_version")
+fw_version = s.query_string_value(mb_path+"/fw_version")
+
+print "FPGA bitstream version: %s" % fpga_version
+print "ZPU firmware version: %s" % fw_version
+
+s.close()

host/utils/umtrx_vswr.py

@@ -46,6 +46,8 @@ class umtrx_vswr:
     gamma = self._gamma
     if gamma == 1.0:
       return float("inf")
+    elif gamma > 1.0:
+      return float("nan")
     else:
       return (1+gamma)/(1-gamma)
 
@@ -54,15 +56,21 @@ class umtrx_vswr:
     gamma = self._gamma
     if gamma == 1.0:
       return float("-inf")
+    elif gamma > 1.0:
+      return float("nan")
     else:
       return -10.0 * math.log(1.0-gamma*gamma, 10)
 
   def pf_rate(self):
     ''' Estimated reflected power rate, % '''
     gamma = self._gamma
+    if gamma > 1.0:
+      return float("nan")
     return 1.0 - gamma*gamma
 
   def pr_rate(self):
     ''' Estimated reflected power rate, % '''
     gamma = self._gamma
+    if gamma > 1.0:
+      return float("nan")
     return gamma*gamma