mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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65 lines
1.7 KiB
Verilog
65 lines
1.7 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// System bootup order:
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// 0 - Internal POR to reset this block. Maybe control it from CPLD in the future?
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// 1 - Everything in reset
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// 2 - Take RAM Loader out of reset
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// 3 - When RAM Loader done, take processor and wishbone out of reset
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module system_control
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(input wb_clk_i,
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output reg ram_loader_rst_o,
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output reg wb_rst_o,
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input ram_loader_done_i
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);
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reg POR = 1'b1;
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reg [3:0] POR_ctr;
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initial POR_ctr = 4'd0;
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always @(posedge wb_clk_i)
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if(POR_ctr == 4'd15)
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POR <= 1'b0;
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else
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POR_ctr <= POR_ctr + 4'd1;
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always @(posedge POR or posedge wb_clk_i)
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if(POR)
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ram_loader_rst_o <= 1'b1;
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else
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ram_loader_rst_o <= #1 1'b0;
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// Main system reset
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reg delayed_rst;
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always @(posedge POR or posedge wb_clk_i)
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if(POR)
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begin
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wb_rst_o <= 1'b1;
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delayed_rst <= 1'b1;
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end
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else if(ram_loader_done_i)
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begin
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delayed_rst <= 1'b0;
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wb_rst_o <= delayed_rst;
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end
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endmodule // system_control
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